User manual
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Document Number: 38-12012 Rev. *O Page 10 of 53
28-Pin Part Pinout
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, SOIC
Pin No.
Type
Pin
Name
Description
Figure 5. CY8C27443 28-Pin PSoC Device
Digital Analog
1 I/O I P0[7] Analog column mux input.
2 I/O I/O P0[5] Analog column mux input and column output.
3 I/O I/O P0[3] Analog column mux input and column output.
4 I/O I P0[1] Analog column mux input.
5 I/O P2[7]
6 I/O P2[5]
7 I/O I P2[3] Direct switched capacitor block input.
8 I/O I P2[1] Direct switched capacitor block input.
9 Power SMP Switch Mode Pump (SMP) connection to external
components required.
10 I/O P1[7] I2C Serial Clock (SCL).
11 I/O P1[5] I2C Serial Data (SDA).
12 I/O P1[3]
13 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
14 Power Vss Ground connection.
15 I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
16 I/O P1[2]
17 I/O P1[4] Optional External Clock Input (EXTCLK).
18 I/O P1[6]
19 Input XRES Active high external reset with internal pull down.
20 I/O I P2[0] Direct switched capacitor block input.
21 I/O I P2[2] Direct switched capacitor block input.
22 I/O P2[4] External Analog Ground (AGND).
23 I/O P2[6] External Voltage Reference (VRef).
24 I/O I P0[0] Analog column mux input.
25 I/O I/O P0[2] Analog column mux input and column output.
26 I/O I/O P0[4] Analog column mux input and column output.
27 I/O I P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programma-
ble System-on-Chip Technical Reference Manual for details.
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2 C SC L , P1 [7 ]
I2 C SD A, P1 [5 ]
P1[3]
I2 C SC L , XT AL in , P1 [1 ]
Vss
Vd d
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TQFP
P3[1]
P2[7]
P2[5] P2[4], External AGND
A, I, P2[3] P2[2], A, I
A, I, P2[1] P2[0], A, I
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
P4[1]
P4[0]
SMP X RE S
P3[7]
P3[6]
P3[5] P3[4]
P3[3] P3[2]
I2C SCL, P1[7]
P0[1], A, I
I2C SDA, P1[5]
P0[3], A, IO
P1[3]
P0[5], A, IO
I2C SCL, XTALin, P1[1]
P0[7], A, I
Vss
Vdd
I2C SDA, XTALout, P1[0]
P0[6], A, I
P1[2]
P0[4], A, IO
EXTCLK, P1[4]
P0[2], A, IO
P1[6]
P0[0], A, I
P3[0]
P2[6], External VRef
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
13
14
15
16
17
18
19
20
21
22
12
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