Specifications

CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. AH Page 43 of 64
10.4.10 AC I
2
C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  T
A
 85 °C, or 3.0 V to 3.6 V and –40 °C  T
A
 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Figure 14. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 36. AC Characteristics of the I
2
C SDA and SCL Pins for V
DD
Symbol Description
Standard Mode Fast Mode
Units Notes
Min Max Min Max
F
SCLI2C
SCL clock frequency 0 100 0 400 kHz
t
HDSTAI2C
Hold time (repeated) start condition. After this
period, the first clock pulse is generated
4.0 –0.6–µs
t
LOWI2C
Low period of the SCL clock 4.7 –1.3–µs
t
HIGHI2C
High period of the SCL clock 4.0 –0.6–µs
t
SUSTAI2C
Setup time for a repeated start condition 4.7 –0.6–µs
t
HDDATI2C
Data hold time 0 –0–µs
t
SUDATI2C
Data setup time 250 – 100
[28]
–ns
t
SUSTOI2C
Setup time for stop condition 4.0 –0.6–µs
t
BUFI2C
Bus free time between a stop and start condition 4.7 –1.3–µs
t
SPI2C
Pulse width of spikes suppressed by the input
filter
– – 0 50 ns
I2C_SDA
I2C_SCL
S
Sr
SP
T
BUFI2C
T
SPI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
START Condition Repeated START Condition
STOP Condition
Note
28. A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU;DAT
250 ns it must meet. This automatically is the case if the
device does not stretch the LOW period of the SCL signal. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I
2
C-bus specification) before the SCL line is released.