Specifications
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. AH Page 40 of 64
10.4.5 AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C T
A
85 °C or 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters are measured at 5 V at 25 °C
and are for design guidance only.
10.4.6 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C T
A
85 °C, or 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 30. AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
t
RLPC
LPC response time – – 50 µs 50 mV overdrive comparator
reference set within V
REFLPC
.
Table 31. AC Digital Block Specifications
Function Description Min Typ Max Unit Notes
All functions Block input clock frequency
V
DD
4.75 V – – 49.92 MHz
V
DD
< 4.75 V – – 25.92 MHz
Timer Input clock frequency
No capture, V
DD
4.75 V – – 49.92 MHz
No capture, V
DD
< 4.75 V – – 25.92 MHz
With capture – – 25.92 MHz
Capture pulse width 50
[26]
––ns
Counter Input clock frequency
No enable input, V
DD
4.75 V – – 49.92 MHz
No enable input, V
DD
< 4.75 V – – 25.92 MHz
With enable input – – 25.92 MHz
Enable input pulse width 50
[26]
––ns
Kill pulse width
Asynchronous restart mode 20 – – ns
Synchronous restart mode 50
[26]
––ns
Disable mode 50
[26]
––ns
Input clock frequency
V
DD
4.75 V – – 49.92 MHz
V
DD
< 4.75 V – – 25.92 MHz
CRCPRS
(PRS
Mode)
Input clock frequency
V
DD
4.75 V – – 49.92 MHz
V
DD
< 4.75 V – – 25.92 MHz
CRCPRS
(CRC
Mode)
Input clock frequency – – 24.6 MHz
SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.1 MHz The input clock is the SPI SCLK in SPIS mode.
Width of SS_negated between
transmissions
50
[26]
––ns
Note
26. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).