Specifications

CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. AH Page 36 of 64
10.4 AC Electrical Characteristics
10.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C  T
A
 85 C, or 3.0 V to 3.6 V and –40 C  T
A
 85 C, respectively. Typical parameters are measured at 5 V and
3.3 V at 25 C and are for design guidance only.
Table 25. AC Chip Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO245V
Internal main oscillator frequency for 24 MHz
(5 V)
23.04 24 24.96
[22]
MHz Trimmed for 5 V operation using
factory trim values.
F
IMO243V
Internal main oscillator frequency for 24 MHz
(3.3 V)
22.08 24 25.92
[23]
MHz Trimmed for 3.3 V operation using
factory trim values.
F
IMOUSB5V
Internal main oscillator frequency with USB
(5 V)
Frequency locking enabled and USB traffic
present.
23.94 24 24.06 MHz –10 °C  T
A
 85 °C
4.35  V
DD
 5.15
F
IMOUSB3V
Internal main oscillator frequency with USB
(3.3 V)
Frequency locking enabled and USB traffic
present.
23.94 24 24.06 MHz –0 °C  T
A
 70 °C
3.15  V
DD
 3.45
F
CPU1
CPU frequency (5 V nominal) 0.093 24 24.96
[22]
MHz SLIMO Mode = 0.
F
CPU2
CPU frequency (3.3 V nominal) 0.086 12 12.96
[23]
MHz SLIMO Mode = 0.
F
BLK5
Digital PSoC block frequency (5 V nominal) 0 48 49.92
[22,24]
MHz Refer to the AC digital block
Specifications.
F
BLK3
Digital PSoC block frequency (3.3 V nominal) 0 24 25.92
[24]
MHz
F
32K1
Internal low speed oscillator frequency 15 32 64 kHz
F
32K_U
Internal low speed oscillator untrimmed
frequency
5 – 100 kHz After a reset and before the M8C
starts to run, the ILO is not trimmed.
See the System Resets section of
the PSoC Technical Reference
Manual for details on this timing
t
XRST
External reset pulse width 10 – – µs
DC24M 24 MHz duty cycle 40 50 60 %
DC
ILO
Internal low speed oscillator duty cycle 20 50 80 %
Step24M 24 MHz trim step size – 50 – kHz
Fout48M 48 MHz output frequency 46.08 48.0 49.92
[22,23]
MHz Trimmed. Utilizing factory trim
values.
F
MAX
Maximum frequency of signal on row input or
row output.
– – 12.96 MHz
SR
POWER_UP
Power supply slew rate – – 250 V/ms V
DD
slew rate during power-up.
t
POWERUP
Time from end of POR to CPU executing code – 16 100 ms Power-up from 0 V. See the System
Resets section of the PSoC
Technical Reference Manual.
t
jit_IMO
[25]
24 MHz IMO cycle-to-cycle jitter (RMS) – 200 1200 ps
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
– 900 6000 ps N=32
24 MHz IMO period jitter (RMS) – 200 900 ps
Notes
22. 4.75 V
< V
DD
< 5.25 V.
23. 3.0 V < V
DD
< 3.6 V. See application note Adjusting PSoC
®
Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
24. See the individual user module datasheets for information on maximum frequencies for user modules.
25. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.