Specifications

CY8C24223A, CY8C24423A
Document Number: 001-52469 Rev. *H Page 28 of 50
Figure 7. PLL Lock Timing Diagram
Figure 8. PLL Lock for Low Gain Setting Timing Diagram
Figure 9. External Crystal Oscillator Startup Timing Diagram
24 MHz
F
PLL
PLL
Enable
T
PLLSLEW
PLL
Gain
0
t
24 MHz
F
PLL
PLL
Enable
T
PLLSLEWLOW
PLL
Gain
1
t
32 kHz
F
32K2
32K
Select
T
OS
t