Datasheet

26 PSoC Designer IDE Guide, Document # 001-42655 Rev *B
Chip-Level Editor
Trip Voltage [LVD (SMP)]
A precision POR circuit is integrated into the PSoC. This parameter allows the user to select voltage
levels that the PSoC uses to internally monitor its supply voltage. Two levels are specified in the
parameter with the syntax <LVD (SMP)>. LVD is the value at which the internal low voltage compar-
ator asserts its control signal. SMP is the level at which the integrated switch mode pump is enabled.
Although selection of SMP is implicit in the selection of LVD, if no switch mode pump circuitry is
used, the part is reset if supply voltage falls too low. At the point when the supply voltage exceeds
the threshold level, the part resumes operation as if the power was switched off and on (POR). Fur-
ther discussion of the switch mode pump and low voltage detect is found in the PSoC Technical Ref-
erence Manual.
USB Clock
Selects the source for the USB SIE.
USB Clock/2
This option divides the USB clock source by 2 when the source is an external crystal oscillator.
When the USB clock is the internal 24 MHz Oscillator, then the divide by 2 is always enabled.
V Keep-alive
Allows voltage regulator to source upto 20 µA of current when the voltage regulator is disabled.
V Reg
A 3.3 V regulator output is placed on the pin P1[2] when Enabled, and when Vcc is above 4.35 V. A
1 µF min, 2 µF max capacitor is required on VREG output.
V Reset
Selects the Power on Reset (POR) voltage level.
VC1 and VC2
These resources are clocks that can be chained to provide various internal clock frequencies used
for digital or analog blocks. A complete discussion of system clocking is found in the PSoC Technical
Reference Manual.
VC3_Source and VC3_Divider
VC3 is a system clock resource similar to the VC1 and VC2 resources. The main difference between
it and VC1 and VC2 is that VC3 may be chained from one of several clock sources and may not be
used as an input clock as flexibly as VC1 and VC2. You cannot use it as a direct input to the analog
section of the PSoC. It can be used as an input to a digital PSoC block and then used to derive a
clock that can be used in many more places. For this reason, it is important to evaluate clocking
options as a PSoC design is being developed. Often, rearranging clock sources according to where
they are most easily connected solves clocking problems. A complete discussion of system clocking
is found in the PSoC Technical Reference Manual.
Watchdog Enable
This parameter activates the Watchdog Timer. The Watchdog Timer is based on a counter that
counts three sleep timer events. To prevent system reset, you must clear this counter before three
sleep timer state events occur, or the PSoC is internally reset. The duration of each sleep timer
event is selected using the Sleep_Timer parameter in the Global Resources frame of PSoC