Specifications

5. Demonstration Projects LIN Bus 2.0 Reference Design
46 Cypress Semiconductor – Rev. ** October 25, 2006
}
SlaveResp: 61 { //pub: any slave
SlaveRespB0, 0;
SlaveRespB1, 8;
SlaveRespB2, 16;
SlaveRespB3, 24;
SlaveRespB4, 32;
SlaveRespB5, 40;
SlaveRespB6, 48;
SlaveRespB7, 56;
}
}
Node_attributes{
DIA {
LIN_protocol = "2.0";
configured_NAD = 0x02;
product_id = 0x1234, 0x2346, 0x00;
response_error = Response_Error_DIA;
P2_min = 5.000 ms;
ST_min = 3.000 ms;
configurable_frames {
VL1_CEM_Frm1 = 0x1001;
VL1_DIA_Frm1 = 0x1002;
}
}
CPM {
LIN_protocol = "2.0";
configured_NAD = 0x01;
product_id = 0x1234, 0x2345, 0x00;
response_error = Response_Error_CPM;
P2_min = 5.000 ms;
ST_min = 3.000 ms;
configurable_frames {
VL1_CEM_Frm1 = 0x1001;
VL1_CPM_Frm1 = 0x1002;
VL1_CPM_Frm2 = 0x1003;
}
}
}
Schedule_tables {
VL1_Fr1_19200 {
VL1_CEM_Frm1 delay 15.00 ms;
VL1_DIA_Frm1 delay 10.00 ms;
VL1_CPM_Frm1 delay 10.0 ms;
VL1_CPM_Frm2 delay 10.0 ms;
}
Initialization {
AssignFrameId{CPM, VL1_CEM_Frm1} delay 2500 ms;
AssignFrameId{CPM, VL1_CPM_Frm1} delay 2500 ms;
AssignFrameId{CPM, VL1_CPM_Frm2} delay 2500 ms;
AssignFrameId{DIA, VL1_CEM_Frm1} delay 2500 ms;
AssignFrameId{DIA, VL1_DIA_Frm1} delay 2500 ms;
}
}