Specifications

5. Demonstration Projects LIN Bus 2.0 Reference Design
44 Cypress Semiconductor – Rev. ** October 25, 2006
5.2.2 Example LDF
LIN Description File Example
/*******************************************/
/* */
/* Description: Example LIN Description */
/* Project: Lin20example */
/* Network: LIN_20 */
/* */
/* *******************************************/
LIN_description_file;
LIN_protocol_version = "2.0";
LIN_language_version = "2.0";
LIN_speed = 19.2 kbps;
Nodes {
master : CEM, 1.000 ms, 0.100 ms;
Slaves: CPM, DIA;
}
Signals {
Switch1CEM : 1, 0, CEM, CPM, DIA;
Switch2CEM : 1, 0, CEM, CPM, DIA;
Switch3CEM : 1, 0, CEM, CPM, DIA;
Switch4CEM : 1, 0, CEM, CPM, DIA;
Switch5CEM : 1, 0, CEM, CPM, DIA;
Switch6CEM : 1, 0, CEM, CPM, DIA;
Switch7CEM : 1, 0, CEM, CPM, DIA;
Switch8CEM : 1, 0, CEM, CPM, DIA;
Resistance : 15, 0, CPM, CEM;
Switch1CPM : 1, 0, CPM, CEM;
Switch2CPM : 1, 0, CPM, CEM;
Switch3CPM : 1, 0, CPM, CEM;
Switch4CPM : 1, 0, CPM, CEM;
Switch5CPM : 1, 0, CPM, CEM;
Switch6CPM : 1, 0, CPM, CEM;
Switch7CPM : 1, 0, CPM, CEM;
Switch8CPM : 1, 0, CPM, CEM;
Switch1DIA : 1, 0, DIA, CEM;
Switch2DIA : 1, 0, DIA, CEM;
LeftIndicator : 1, 0, CEM, DIA;
RightIndicator : 1, 0, CEM, DIA;
Response_Error_CPM : 1, 0, CPM, CEM;
Response_Error_DIA : 1, 0, DIA, CEM;
}
Diagnostic_signals {
MasterReqB0:8,0;
MasterReqB1:8,0;
MasterReqB2:8,0;
MasterReqB3:8,0;
MasterReqB4:8,0;
MasterReqB5:8,0;
MasterReqB6:8,0;
MasterReqB7:8,0;
SlaveRespB0:8,0;
SlaveRespB1:8,0;
SlaveRespB2:8,0;
SlaveRespB3:8,0;