Specifications

October 25, 2006 Cypress Semiconductor – Rev. ** 41
LIN Bus 2.0 Reference Design 4. Slave Design IP
The overall CPU overhead for a frame is calculated by add-
ing all the time components for a frame and then finding the
fraction on the total frame time. Remember, this method only
provides the overall overhead. At some instances, the CPU
overhead is quite high, especially inside the GPIO ISR. As a
result, calculate the CPU overhead taking into account the
time between successive interrupts and the time taken
inside any particular branch of the GPIO ISR.
4.8.2 Calculation of CPU Overhead Over
a Frame
These calculations are based upon a baud rate of 19.2 kbps
and CPU speed of 24 MHz. For lower baud rates, the CPU
overhead is less.
Example 1: A frame of 1 byte being received.
Total time for Break/Synch = 224 µS.
Known ID received, RX initialized = 16 µS.
1 byte to received = 7 µS.
Frame reception complete (checksum received) = 73 µS.
Total time = 320 µS.
Total bits in frame = 54.
Total frame time = 1.4 * 54 * 1/19.2K = 3.93 mS.
Overall CPU overhead = 320 µS / 3.93 mS = 8.14%.
For calculation, the worst case frame length of 1 byte was
used. For an 8-byte frame, the overhead is reduced to 4%.
Example 2: A frame of 1 byte being transmitted
Total time for Break/Synch = 224 µS.
Known ID received, TX initialized = 39 µS.
2 bytes to be transmitted (1 byte + checksum) = 2 * Single
byte transmitted = 14 µS.
All bytes transmitted = 50 µS.
Total time = 327 µS.
Total bits in frame = 54.
Total frame time = 1.4 * 54 * 1/19.2K = 3.9 3 mS.
Overall CPU overhead = 327 µS / 3.93 mS = 8.32%.
For calculation, the worst case frame length of 1 byte was
used. For an 8-byte frame, the overhead is reduced to 4%.
4.8.3 Maximum Interrupt Latency
This is the maximum latency the LIN node causes in an
application. Using the information listed in the tables section
4.8.1, the maximum time taken inside the ISR is in the GPIO
ISR when the fourth falling edge was received and this value
is 150 µS. Take this value into consideration when the inter-
rupts of the main application are designed or analyzed.
Table 4-6. TxInterrupt
Sl. No. Stage No. Of Cycles
Time(µS)
1 When a byte has been sent 166 6.92
2 When last byte has been sent 130 5.42
Table 4-7. TxBitTimerInterrupt
Sl. No. Stage No. Of Cycles
Time(µS)
1 All bytes transmitted 1200 50.00
Table 4-8. Other Functions
Sl. No. Stage No. Of Cycles
Time(µS)
1 LoadSynchroReceptionConfiguration 790 32.92
2 LoadDataReceptionConfiguration 768 32.00
3 LoadDataTransmissionConfiguration 153 6.38