Datasheet

CY8C21x34B
Document Number: 001-67345 Rev. *E Page 37 of 49
Thermal Impedances
Solder Reflow Peak Temperature
Tab le 35 lists the maximum solder reflow peak temperatures to achieve good solderability. Thermal ramp rate during preheat should
be 3 °C/s or lower.
Table 34. Thermal Impedances per Package
Package Typical
JA
[28]
Typical
JC
16-pin SOIC 123 °C/W 55 °C/W
20-pin SSOP 117 °C/W 41 °C/W
28-pin SSOP 96 °C/W 39 °C/W
32-pin QFN
[29]
5 × 5 mm 0.60 Max 27 °C/W 15 °C/W
32-pin QFN
[29]
5 × 5 mm 0.93 Max 22 °C/W 12 °C/W
56-pin SSOP 48 °C/W 24 °C/W
Table 35. Solder Reflow Peak Temperature
Package Maximum Peak Temperature Time at Maximum Temperature
16-pin SOIC 260 °C 30 s
20-pin SSOP 260 °C 30 s
28-pin SSOP 260 °C 30 s
32-pin QFN 260 °C 30 s
56-pin SSOP 260 °C 30 s
Notes
28. T
J
= T
A
+ Power ×
JA
29. To achieve the thermal impedance specified for the QFN package, refer to Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices
– AN72845
available at http://www.cypress.com.
30. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5
C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.