Datasheet

CY8C21x34B
Document Number: 001-67345 Rev. *E Page 32 of 49
AC Programming Specifications
Tab le 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C T
A
85 °C, or 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V
at 25 °C and are for design guidance only.
AC I
2
C Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C T
A
85 °C, 3.0 V to 3.6 V and –40 °C T
A
85 °C, or 2.4 V to 3.0 V and –40 °C T
A
85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 31. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
T
RSCLK
Rise time of SCLK 1 20 ns
T
FSCLK
Fall time of SCLK 1 20 ns
T
SSCLK
Data setup time to falling edge of SCLK 40 ns
T
HSCLK
Data hold time from falling edge of SCLK 40 ns
F
SCLK
Frequency of SCLK 0 8 MHz
T
ERASEB
Flash erase time (block) 10 ms
T
WRITE
Flash block write time 40 ms
T
DSCLK
Data out delay from falling edge of SCLK 45 ns 3.6 V
DD
T
DSCLK3
Data out delay from falling edge of SCLK 50 ns 3.0 V
DD
3.6
T
DSCLK2
Data out delay from falling edge of SCLK 70 ns 2.4 V
DD
3.0
T
ERASEALL
Flash erase time (Bulk) 20 ms Erase all blocks and protection
fields at once
T
PROGRAM_HOT
Flash block erase + flash block write time 100
[26]
ms 0 °C Tj 100 °C
T
PROGRAM_COLD
Flash block erase + flash block write time 200
[26]
ms –40 °C Tj 0 °C
Table 32. AC Characteristics of the I
2
C SDA and SCL Pins for V
DD
3.0 V
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
F
SCLI2C
SCL clock frequency 0 100 0 400 kHz
T
HDSTAI2C
Hold time (repeated) start condition. After this
period, the first clock pulse is generated
4.0 –0.6–µs
T
LOWI2C
Low period of the SCL clock 4.7 –1.3–µs
T
HIGHI2C
High period of the SCL clock 4.0 –0.6–µs
T
SUSTAI2C
Setup time for a repeated start condition 4.7 –0.6–µs
T
HDDATI2C
Data hold time 0 –0–µs
T
SUDATI2C
Data setup time 250 100
[27]
–ns
T
SUSTOI2C
Setup time for stop condition 4.0 –0.6–µs
T
BUFI2C
Bus free time between a stop and start condition 4.7 –1.3–µs
T
SPI2C
Pulse width of spikes suppressed by the input
filter.
–050ns
Notes
26. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC
®
Flash) for more information.
27. A Fast-Mode I
2
C-bus device may be used in a Standard-Mode I
2
C-bus system, but it must meet the requirement T
SU;DAT
250 ns. This is automatically the case if
the device does not stretch the LOW period of the SCL signal. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line T
rmax
+ T
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I
2
C-bus specification) before the SCL line is released.