Datasheet

CY8C21x34B
Document Number: 001-67345 Rev. *E Page 15 of 49
20 I/O P3[1]
21 NC No connection
22 NC No connection
23 I/O P1[7] I
2
C SCL
24 I/O P1[5] I
2
C SDA
25 NC No connection
26 I/O P1[3] I
FMTEST
27 I/O P1[1] I
2
C SCL, ISSP-SCLK
[8]
28 Power V
SS
Ground connection
29 NC No connection
30 NC No connection
31 I/O P1[0] I
2
C SDA, ISSP-SDATA
[8]
32 I/O P1[2] V
FMTEST
33 I/O P1[4] Optional external clock input (EXTCLK)
34 I/O P1[6]
35 NC No connection
36 NC No connection
37 NC No connection
38 NC No connection
39 NC No connection
40 NC No connection
41 Input XRES Active high external reset with internal pull-down
42 OCD HCLK OCD high-speed clock output
43 OCD CCLK OCD CPU clock output
44 I/O P3[0]
45 I/O P3[2]
46 NC No connection
47 NC No connection
48 I/O IP2[0]
49 I/O IP2[2]
50 I/O P2[4]
51 I/O P2[6]
52 I/O I P0[0] Analog column mux input
53 I/O I P0[2] Analog column mux input and column output
54 I/O I P0[4] Analog column mux input and column output
55 I/O I P0[6] Analog column mux input
56 Power V
DD
Supply voltage
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Table 6. Pin Definitions – CY8C21001 56-Pin (SSOP) (continued)
Pin No.
Type
Pin Name Description
Digital Analog
Note
8. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.