CY8C21x34B ® PSoC Programmable System-on-Chip™ CapSense Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity ® Features ■ ❐ Advanced CapSense block with SmartSense Auto-Tuning ❐ Patented CSD sensing algorithm ❐ SmartSense_EMC Auto-Tuning • Sets and maintains optimal sensor performance during run time • Eliminates system tuning during development and production • Compensates for variations in manufacturing process ■ Driven shield ❐ Delivers best-in class water tolerant designs
CY8C21x34B More Information Note: For CY8C21x34B devices related Development Kits please click here. Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article “How to Design with PSoC® 1, PowerPSoC®, and PLC – KBA88292”.
CY8C21x34B Contents PSoC Functional Overview .............................................. 4 The PSoC Core ........................................................... 4 The Digital System ...................................................... 4 The Analog System ..................................................... 5 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 6 Development Tools .....................................
CY8C21x34B PSoC Functional Overview The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.
CY8C21x34B The Analog System The Analog Multiplexer System The analog system consists of four configurable blocks that allow for the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are: The analog mux bus can connect to every GPIO pin. Pins may be connected to the bus individually or in any combination.
CY8C21x34B PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted in Table 1. Table 1.
CY8C21x34B Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment.
CY8C21x34B Designing with PSoC Designer Generate, Verify, and Debug The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions.
CY8C21x34B Pin Information The CY8C21x34B PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O. 16-Pin Part Pinout Figure 4.
CY8C21x34B 20-Pin Part Pinout Figure 5. CY8C21334B 20-Pin PSoC Device A, I, M, P0[7] 1 20 VDD A, I, M, P0[5] 2 19 P0[6], A, I, M A, I, M, P0[3] 3 18 P0[4], A, I, M A, I, M, P0[1] 4 17 P0[2], A, I, M VSS 5 16 P0[0], A, I, M M, I2C SCL, P1[7] 6 15 XRES M, I2C SDA, P1[5] 7 14 P1[6], M M, P1[3] 8 13 P1[4], EXTCLK, M M, I2C SCL, P1[1] 9 12 P1[2], M VSS 10 11 P1[0], I2C SDA, M SSOP Table 3. Pin Definitions – CY8C21334B 20-Pin (SSOP) Pin No.
CY8C21x34B 28-Pin Part Pinout Figure 6.
CY8C21x34B 32-Pin Part Pinout Figure 7. CY8C21434B 32-Pin PSoC Device Figure 9. CY8C21634B 32-Pin Sawn PSoC Device Sawn M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] Document Number: 001-67345 Rev.
CY8C21x34B Table 5. Pin Definitions - CY8C21434B/CY8C21634B 32-Pin (QFN)[6] Pin No.
CY8C21x34B 56-Pin Part Pinout The 56-Pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Figure 10.
CY8C21x34B Table 6. Pin Definitions – CY8C21001 56-Pin (SSOP) (continued) Type Pin No.
CY8C21x34B Register Reference This chapter lists the registers of the CY8C21x34B PSoC device. For detailed register information, see the PSoC Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in Table 7. Table 7.
CY8C21x34B Table 8.
CY8C21x34B Table 9.
CY8C21x34B Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C21x34B PSoC device. For up-to-date electrical specifications, visit the Cypress web site at http://www.cypress.com. Specifications are valid for –40 C TA 85 C and TJ 100 C as specified, except where noted. Refer to Table 21 on page 26 for the electrical specifications for the IMO using SLIMO mode. Figure 14. IMO Frequency Trim Options Figure 11.
CY8C21x34B Operating Temperature Symbol Description TA Ambient temperature TJ Junction temperature Min –40 –40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See Table 34 on page 37. You must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip-Level Specifications Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.
CY8C21x34B DC General-Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 11. 5-V and 3.
CY8C21x34B DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 13.
CY8C21x34B DC Switch Mode Pump Specifications Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Figure 12. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT + SMP Battery C1 PSoC Vss Table 16.
CY8C21x34B Table 16. DC Switch Mode Pump (SMP) Specifications (continued) Symbol Description Min Typ Max Units Notes For I load = 1mA, VPUMP = 2.55 V, VBAT = 1.3 V, 10 µH inductor, 1 µF capacitor, and Schottky diode E2 Efficiency 35 80 – % FPUMP Switching frequency – 1.3 – MHz DCPUMP Switching duty cycle – 50 – % DC Analog Mux Bus Specifications Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.
CY8C21x34B DC Programming Specifications Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 19. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5 Max 5.
CY8C21x34B AC Electrical Characteristics AC Chip-Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 21. 5-V and 3.
CY8C21x34B Table 22. 2.7-V AC Chip-Level Specifications Symbol FIMO12 Description IMO frequency for 12 MHz Min 11.5 Typ 120 Max 12.7[21,22] Units MHz FIMO6 IMO frequency for 6 MHz 5.5 6 6.5[21,22] MHz FCPU1 CPU frequency (2.7 V nominal) 0.093 3 3.15[21] MHz FBLK27 Digital PSoC block frequency (2.7 V nominal) 0 12 12.5[21,22] MHz F32K1 F32K_U ILO frequency ILO untrimmed frequency 8 5 32 – 96 100 kHz kHz tXRST DCILO FMAX 10 20 – – 50 – – 80 12.
CY8C21x34B AC General Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 23. 5-V and 3.
CY8C21x34B AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 26. 5-V and 3.
CY8C21x34B Table 27. 2.7-V AC Digital Block Specifications Function Description All functions Block input clock frequency Timer Capture pulse width Input clock frequency, with or without capture Counter Typ Max Units Notes – – 12.7 MHz 2.4 V < VDD < 3.0 V 100[25] – – ns – – 12.7 MHz 100 – – ns Input clock frequency, no enable input – – 12.7 MHz Input clock frequency, enable input – – 12.
CY8C21x34B Table 29. 3.3-V AC External Clock Specifications Min Typ Max Units Notes FOSCEXT Symbol Frequency with CPU clock divide by 1 Description 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements FOSCEXT Frequency with CPU clock divide by 2 or greater 0.186 – 24.
CY8C21x34B AC Programming Specifications Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 31.
CY8C21x34B Table 33. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated.
CY8C21x34B Packaging Information This section shows the packaging specifications for the CY8C21x34B PSoC device with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 15. 16-Pin (150-Mil) SOIC 51-85068 *E Figure 16. 20-Pin (210-Mil) SSOP 51-85077 *E Document Number: 001-67345 Rev.
CY8C21x34B Figure 17. 28-Pin (210-Mil) SSOP 51-85079 *E Figure 18. 32-Pin QFN ( 5 X 5 X 1.0 MM) LT32B (3.5 X 3.5) EPAD (SAWN) 001-30999 *D Document Number: 001-67345 Rev.
CY8C21x34B Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) 1.3 × 2.7 E-Pad (Sawn Type) Package Outline 001-48913 *D Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note, Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at http://www.cypress.com. Figure 20. 56-Pin (300-Mil) SSOP 51-85062 *F Document Number: 001-67345 Rev.
CY8C21x34B Thermal Impedances Table 34. Thermal Impedances per Package Typical JA [28] 123 °C/W 117 °C/W 96 °C/W 27 °C/W 22 °C/W 48 °C/W Package 16-pin SOIC 20-pin SSOP 28-pin SSOP 32-pin QFN[29] 5 × 5 mm 0.60 Max 32-pin QFN[29] 5 × 5 mm 0.93 Max 56-pin SSOP Typical JC 55 °C/W 41 °C/W 39 °C/W 15 °C/W 12 °C/W 24 °C/W Solder Reflow Peak Temperature Table 35 lists the maximum solder reflow peak temperatures to achieve good solderability. Thermal ramp rate during preheat should be 3 °C/s or lower.
CY8C21x34B Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C21x34B family. Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of cost at http://www.cypress.com and includes a free C compiler.
CY8C21x34B Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer ■ MiniProg programming unit The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ PSoC Designer software CD ■ Getting Started guide ■ USB 2.
CY8C21x34B SRAM (Bytes) Switch Mode Pump Temperature Range Digital Blocks Analog Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin 16-Pin (150-Mil) SOIC CY8C21234B-24SXI 8K 512 Yes –40 °C to +85 °C 4 4 12 12[33] 0 No 16-Pin (150-Mil) SOIC (Tape and Reel) CY8C21234B-24SXIT 8K 512 Yes –40 °C to +85 °C 4 4 12 12[33] 0 No 20-Pin (210-Mil) SSOP CY8C21334B-24PVXI 8K 512 No –40 °C to +85 °C 4 4 16 16[33] 0 Yes [33] 0 Yes Package Ordering Code Flash (By
CY8C21x34B Acronyms Table 37 lists the acronyms that are used in this document. Table 37.
CY8C21x34B Document Conventions Units of Measure Table 38 lists the units of measures. Table 38.
CY8C21x34B Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2.
CY8C21x34B Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. External Reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state.
CY8C21x34B Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller.
CY8C21x34B Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface.
CY8C21x34B Document History Page Document Title: CY8C21x34B, PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity Document Number: 001-67345 Revision ECN Orig. of Change Submission Date Description of Change ** 3169205 YVA 02/16/2011 New data sheet. *A 3247292 YVA 05/11/2011 Updated Packaging Information. Post to Web. *B 3846480 SRLI 12/19/2012 Updated Features.
CY8C21x34B Document History Page (continued) Document Title: CY8C21x34B, PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity Document Number: 001-67345 Revision ECN Orig.
CY8C21x34B Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.
