Datasheet

CY8C21x34/B CapSense
®
Design Guide Document No. 001-66271 Rev. *B 53
8.2 Post Wakeup Execution Sequence
If the CapSense controller is awakened through a reset, then execution starts at the beginning of the boot code. If the
CapSense controller is awakened by an interrupt service routine, the first instruction to execute is the one
immediately following the sleep instruction. This is because the instruction immediately following the sleep instruction
is prefetched before the CapSense controller is fully asleep. Therefore, if global interrupts are disabled, the instruction
execution will continue where it left off before sleep was initiated.
8.2.1 PLL Mode Enabled
If PLL mode is enabled, the CPU frequency must be reduced to the minimum of 3 MHz before going to sleep. This is
because the PLL always overshoots as it attempts to relock after the CapSense controller wakes up and is re-
enabled. Additionally, you should wait 10 ms after wakeup before normal CPU operation begins to ensure proper
execution. This implies that, to use sleep mode and the PLL, the software must be able to execute at 3 MHz. A
simple write to the OSC_CR0 register can reduce CPU speed. However, this register just sets a divider of SYSCLK,
which means that the CPU speed will vary between part families with different SYSCLKs. Typically, SYSCLK is
24 MHz
OSC_CR0 &= 0xf8; // CPU = 3 IMO = 24
8.2.2 Execution of Global Interrupt Enable
It is not desirable to get an interrupt on the instruction boundary of writing the SLEEP bit. This could cause all
firmware preparations for going to sleep to be bypassed, if a sleep command is executed on a return from interrupt
(reti) instruction. To prevent this, interrupts are temporarily disabled before sleep preparations and then re-enabled
before going to sleep. Because of the timing of the Global Interrupt instruction, an interrupt cannot occur during the
next instruction, which in this case is setting the SLEEP bit.
8.2.3 I
2
C Slave with Sleep Mode
There are a few complications using an I
2
C Slave in sleep mode. Because the IMO and CPU are shut off during
sleep, there is no processing within the CapSense controller. The problem arises with the I
2
C address. When an I
2
C
START condition is sent to a particular address, the CapSense controller cannot process the address and therefore
responds with a NAK. A typical workaround is to set up falling edge interrupts on either the clock or data lines of the
I
2
C bus. The master can then send a dummy START condition to wake up the CapSense controller. There is some
lag time between waking up and being able to process an I
2
C address, so the master may need to delay up to 200 µs
before the next transmission or continue to send until an ACK is received. This solution has a second problem in that
the CapSense controller will wake up on any I
2
C falling edge traffic, which causes more total active time and higher
sleep currents. Another solution is to use a third GPIO pin to wake up the CapSense controller and then send the
initial START condition after the appropriate delay time.
8.2.4 Sleep Timer
The CapSense controller offers a sleep timer and a Sleep Timer User Module. These are used while CapSense
controller is asleep and both perform similar functions. The actual sleep timer runs off of the internal low-speed
oscillator, which is never turned off. At selectable intervals of 1 Hz, 8 Hz, 64 Hz, and 512 Hz, the timer generates an
interrupt. It is often useful to periodically wake the CapSense controller up to do some processing or check for
activity. An example of this would be to periodically wake up to scan a sensor. The Sleep Timer User Module uses
the sleep timer to generate some additional functionality. This functionality includes a background tick counter to
generate periodic interrupts, a delay function for program loops, a settable down counter, and a loop governor to
control loop time. A simple block diagram for this functionality is shown in Figure 8-1.