Datasheet

CY8C21x34/B CapSense
®
Design Guide Document No. 001-66271 Rev. *B 51
8. Low Power Design Considerations
Power consumption is an important aspect of microcontroller designs. Among the several techniques to reduce the
average current used by the CapSense controller, sleep mode is the most popular. The CapSense controller uses
sleep mode when it is not required to perform any function, similar to a cell phone backlight dimming after an idle
period. This is done to reduce the average current consumed by the device, a necessity of all battery applications.
The CapSense controller enters sleep mode by writing a ‘1’ to the SLEEP bit within the CPU_SCR0 register (Bit 3).
This is accomplished by calling the M8C_Sleep macro. While in sleep mode, the central CPU is stopped, the internal
main oscillator (IMO) is disabled, the Bandgap Voltage reference is powered down, and the Flash Memory Model is
disabled. The only circuits left in operation are supply voltage monitor and 32-kHz internal oscillator. Power saving
techniques other than sleep mode are:
 Disable CapSense (PSoC) analog block references
 Disable continuous time (CT) and switch capacitor (SC) blocks
 Disable CapSense (PSoC) analog output buffers
 Set drive modes to analog HI-Z
Sleep mode has negative effects for a design. If not used carefully, it can cause unpredictable operation. The PSoC
must be correctly awakened from sleep when necessary, and the user must be aware that the device is sleeping to
allow extra processing.
8.1 Additional Power Saving Techniques
All of the power saving techniques, with the exception of sleep mode, are application based and some of these
produce undesirable results. Each technique is discussed in detail below.
ABF_CR0 &= 0xc3; // Buffer Off
8.1.1 Set Drive Modes to Analog HI-Z
The state of the CapSense controller drive modes can affect power consumption. You can change the drive modes
only on pins that do not cause adverse affects to the system. The change must occur in a sequence that does not
produce line glitches. This sequence depends on the current drive mode of the pin and the state of port data register.
With the CapSense controller drive mode structure, the pin must temporarily be in either Resistive Pull-up or
Resistive Pull-down drive mode when switching between HI-Z or Strong drive modes. The temporary drive mode is
the opposite of the previous value on the pin. So, if the pin was driven high, then the temporary drive mode must be
Resistive Pull-down. This ensures that the drive mode of the pin is not resistive, which eliminates any possible glitch.
The drive modes are set manually in software, before going to sleep. There are three registers, PRTxDM0,
PRTxDM1, and PRTxDM2, which control the drive modes. One bit per register is assigned to a pin. So, to change the
drive mode of a single pin, three register writes are needed. However, this is convenient because an entire port is
changed by the same three register writes. The correct pit pattern for Analog HI-Z is 110b. Use the following code to
set port zero to Analog HI-Z, from Strong, by first going to Resistive Pull-down.
PRT0DM0 = 0x00; // low bits
PRT0DM1 = 0xff; // med bits
PRT0DM2 = 0xff; //high bits