Datasheet

24 Document No. 001-66271 Rev. *B CY8C21x34/B CapSense

Design Guide

3.7.3 Reference

A voltage reference to the input of the comparator is required for the proper operation of CSD.

Possible values are:

 VBG: Internal voltage reference of 1.3 V derived from a fixed bandgap reference.

 ASE11: Internal variable voltage reference derived from a PWM.

 AnalogColumn_InputSelect_1: External voltage reference such as a resistor divider network or externally filtered

PWM/PRSPWM signal. This reference can be connected to a CapSense controller pin and used as the

comparator reference source.

3.7.4 Ref Value

The effect of this parameter depends on the Reference parameter selection. This value has no effect when the

reference comes from the VBG or from AnalogColumn_InputSelect_1. When the reference comes from ASE11, this

parameter sets the reference value.

Possible values are: 0 (minimum ¼V

) to 8 (maximum ¾ V

3.7.5 Prescaler Period

The sensor capacitance is switched continuously between two potentials while scanning. This parameter sets the

prescaler period register and determines the precharge switch output frequency. This parameter is available only for

CSD with the clock prescaler configuration.

Possible values are1 to 255.

3.7.6 Shield Electrode Out

Shield Electrode Out should be enabled for applications requiring water-tolerant performance. The shield electrode

signal source can be selected from one of the free digital row buses (Row_0_Output_1 to Row_0_Output_3). Each

row output can be routed to one of three pins. Set the Row LUT Function to A.

Possible values are Enabled and Disabled.

3.8 CSDADC User Module Configurations

The CSDADC combines capacitance sensing with ADC functionality. It saves code space by reusing modules

common to both the CSD and ADC. You should use the CSDADC when your design requires both capacitance

sensing and ADC functionality. Applications that need one or the other should use the CSD User Module or the ADC8

or ADC10 User Modules.

There are four selectable clock configurations for the CSDADC User Module: PRS16, PWM8, PRS8, and VC2. These

configurations use different signal sources for the switched capacitor circuit on the front end of the CSD

You should select the clock configuration when you first place the CSDADC User Module into your PSoC Designer

project. You can change this selection later by right-clicking the CSDADC User Module and selecting User Module

Selection Options.

3.8.1 CSDADC with PRS16 Clock Source

In this configuration, a 16-bit pseudo-random sequence (PRS) is used as the signal source for the switched-capacitor

circuit on the front end of the CSD. System Clock (IMO) is the clock source for the PRS. The PRS spreads the clock’s

frequency spectrum and provides good noise immunity. This configuration requires three digital blocks.

3.8.2 CSDADC with PRS8 Clock Source

In this configuration, an 8-bit PRS is used as the signal source for the switched-capacitor circuit on the front end of

the CSD. System Clock (IMO) is the clock source for the PRS. The PRS spreads the clock’s frequency spectrum to

give noise immunity. Note that the 16-bit PRS used in the CSD without the Clock Prescaler configuration provides

better noise immunity. This configuration requires three digital blocks.