Datasheet

CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Document Number: 38-12025 Rev. AF Page 29 of 55
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C  T
A
 85 °C, 3.0 V to 3.6 V and –40 °C  T
A
 85 °C, or 2.4 V to 3.0 V and –40 °C  T
A
 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 21. 5-V and 3.3-V AC Digital Block Specifications
Function Description Min Typ Max Unit Notes
All functions Block input clock frequency
V
DD
 4.75 V – – 49.2 MHz
V
DD
< 4.75 V – – 24.6 MHz
Timer Input clock frequency
No capture, V
DD
4.75 V – – 49.2 MHz
No capture, V
DD
< 4.75 V – – 24.6 MHz
With capture – – 24.6 MHz
Capture pulse width 50
[37]
––ns
Counter Input clock frequency
No enable input, V
DD
 4.75 V – – 49.2 MHz
No enable input, V
DD
< 4.75 V – – 24.6 MHz
With enable input – – 24.6 MHz
Enable input pulse width 50
[37]
––ns
Dead Band Kill pulse width
Asynchronous restart mode 20 – – ns
Synchronous restart mode 50
[37]
––ns
Disable mode 50
[37]
––ns
Input clock frequency
V
DD
 4.75 V – – 49.2 MHz
V
DD
< 4.75 V – – 24.6 MHz
CRCPRS
(PRS
Mode)
Input clock frequency
V
DD
 4.75 V – – 49.2 MHz
V
DD
< 4.75 V – – 24.6 MHz
CRCPRS
(CRC
Mode)
Input clock frequency – – 24.6 MHz
SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.1 MHz The input clock is the SPI SCLK in SPIS mode.
Width of SS_negated between
transmissions
50
[37]
––ns
Transmitter Input clock frequency The baud rate is equal to the input clock frequency
divided by 8.
V
DD
 4.75 V, 2 stop bits – – 49.2 MHz
V
DD
 4.75 V, 1 stop bit – – 24.6 MHz
V
DD
< 4.75 V – – 24.6 MHz
Receiver Input clock frequency The baud rate is equal to the input clock frequency
divided by 8.
V
DD
 4.75 V, 2 stop bits – – 49.2 MHz
V
DD
 4.75 V, 1 stop bit – – 24.6 MHz
V
DD
< 4.75 V – – 24.6 MHz
Note
37. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).