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April 20, 2005 Document No. 38-12025 Rev. *G 30
4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/support/link.cfm?mr=poddim.
4.1 Packaging Dimensions
Figure 4-1. 16-Lead (150-Mil) SOIC
DIMENSIONS IN INCHES[MM]
MIN.
MAX.
PIN 1 ID
0.291[7.391]
0.299[7.594]
0.394[10.007]
0.419[10.642]
0.397[10.083]
0.413[10.490]
0.050[1.270]
TYP.
0.092[2.336]
0.105[2.667]
0.004[0.101]
0.0118[0.299]
SEATING PLANE
0.0091[0.231]
0.0125[0.317]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
0.026[0.660]
0.032[0.812]
0.004[0.101]
18
916
*
*
*
*
REFERENCE JEDEC MO-119
PART #
S16.3 STANDARD PKG.
SZ16.3 LEAD FREE PKG.
51-85022 *B