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April 20, 2005 © Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12025 Rev. *G 1

PSoC™ Mixed-Signal Array Final Data Sheet

CY8C21234, CY8C21334,

CY8C21434, CY8C21534, and CY8C21634

PSoC™ Functional Overview

The PSoC™ family consists of many Mixed-Signal Array with

On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components

with one, low cost single-chip programmable component. A

PSoC device includes configurable blocks of analog and digital

logic, as well as programmable interconnect. This architecture

allows the user to create customized peripheral configurations,

to match the requirements of each individual application. Addi-

tionally, a fast CPU, Flash program memory, SRAM data mem-

ory, and configurable IO are included in a range of convenient

pinouts.

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: the Core, the System Resources, the Digital

System, and the Analog System. Configurable global bus

resources allow all the device resources to be combined into a

complete custom system. Each CY8C21x34 PSoC device

includes four digital blocks and four analog blocks. Depending

on the PSoC package, up to 28 general purpose IO (GPIO) are

also included. The GPIO provide access to the global digital

and analog interconnects.

The PSoC Core

The PSoC Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO (inter-

nal main oscillator) and ILO (internal low speed oscillator). The

Features

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds to 24 MHz

❐ Low Power at High Speed

❐ 2.4V to 5.25V Operating Voltage

❐ Operating Voltages Down to 1.0V Using

On-Chip Switch Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC Blocks)

❐ 4 Analog Type “E” PSoC Blocks Provide:

- 2 Comparators with DAC Refs

- Single or Dual 8-Bit 28 Channel ADC

❐ 4 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Full-Duplex UART, SPI™ Master or Slave

- Connectable to All GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Flexible On-Chip Memory

❐ 8K Flash Program Storage 50,000 Erase/Write

Cycles

❐ 512 Bytes SRAM Data Storage

❐ In-System Serial Programming (ISSP™)

❐ Partial Flash Updates

❐ Flexible Protection Modes

❐ EEPROM Emulation in Flash

■ Complete Development Tools

❐ Free Development Software

(PSoC™ Designer)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation

❐ Complex Breakpoint Structure

❐ 128K Trace Memory

■ Precision, Programmable Clocking

❐ Internal ±2.5% 24/48 MHz Oscillator

❐ Internal Oscillator for Watchdog and Sleep

■ Programmable Pin Configurations

❐ 25 mA Drive on All GPIO

❐ Pull Up, Pull Down, High Z, Strong, or Open

Drain Drive Modes on All GPIO

❐ Up to 8 Analog Inputs on GPIO

❐ Configurable Interrupt on All GPIO

■ Versatile Analog Mux

❐ Common Internal Analog Bus

❐ Simultaneous Connection of IO Combinations

❐ Capacitive Sensing Application Capability

■ Additional System Resources

❐ I

C™ Master, Slave and Multi-Master to

400 kHz

❐ Watchdog and Sleep Timers

❐ User-Configurable Low Voltage Detection

❐ Integrated Supervisory Circuit

❐ On-Chip Precision Voltage Reference

DIGITAL SYSTEM

SRAM

512 Bytes

System Bus

Interrupt

Controller

Clock So urces

(Includes IMO and ILO)

Global Digital

Interconnect

Global Analog Interconnect

PSoC

CORE

CPU Core

(M8C)

SROM Flash 8K

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Re f.

Digital

Clocks

I2C

POR and LVD

System Resets

Int er nal

Voltage

Ref .

Sw itch

Mode

Pump

Por t 1 Por t 0

Sleep and

Watchdog

Analog

Mux

Port 3 Por t 2

Analog

PSoC

Block

Array

Digital

PSoC

Block

Array

Summary of content (9 pages)

PAGE 1
PSoC™ Mixed-Signal Array Final Data Sheet CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 Features ■ Flexible On-Chip Memory ■ Powerful Harvard Architecture Processor ❐ 8K Flash Program Storage 50,000 Erase/Write Cycles ❐ 512 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash ❐ ❐ ❐ ❐ M8C Processor Speeds to 24 MHz Low Power at High Speed 2.4V to 5.25V Operating Voltage Operating Voltages Down to 1.
PAGE 2
CY8C21x34 Final Data Sheet PSoC™ Overview Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. Array Input Configuration ACI0[1:0] ■ Digital clock dividers provide three customizable clock frequencies for use in applications.
PAGE 3
CY8C21x34 Final Data Sheet 1.1.4 1. Pin Information 32-Pin Part Pinout Table 1-4. 32-Pin Part Pinout (MLF*) IO M P2[7] 3 IO M P2[5] 4 IO M P2[3] 5 IO M P2[1] 6 IO 6 7 M Power IO 7 M Power P3[3] In CY8C21434 part. SMP Switch Mode Pump (SMP) connection to required external components in CY8C21634 part. P3[1] In CY8C21434 part. Vss Ground connection in CY8C21634 part. 8 IO M P1[7] I2C Serial Clock (SCL). I2C Serial Data (SDA).
PAGE 4
. Packaging Information This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. 4.1 Packaging Dimensions PIN 1 ID 8 1 MIN. MAX.
PAGE 5
CY8C21x34 Final Data Sheet 4. Packaging Information 51-85077 *C Figure 4-2. 20-Lead (210-MIL) SSOP 51-85079 - *C Figure 4-3. 28-Lead (210-Mil) SSOP April 20, 2005 Document No. 38-12025 Rev.
PAGE 6
CY8C21x34 Final Data Sheet 4. Packaging Information 51-85188 ** E-PAD X, Y for this product is 3.71 mm, 3.71 mm (+/-0.08 mm) Figure 4-4. 32-Lead (5x5 mm) MLF Important Note For information on the preferred dimensions for mounting MLF packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. 4.2 Thermal Impedances Table 4-1.
PAGE 7
CY8C21x34 Final Data Sheet 4.3 4. Packaging Information Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 4-2. Solder Reflow Peak Temperature Package Minimum Peak Temperature* Maximum Peak Temperature 16 SOIC 240oC 260oC 20 SSOP 240oC 260oC 28 SSOP 240oC 260oC 32 MLF 240oC 260oC *Higher temperatures may be required based on the solder melting point.
PAGE 8
5. Ordering Information The following table lists the CY8C21x34 PSoC device’s key package features and ordering codes.
PAGE 9
6. Sales and Service Information To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information. Cypress Semiconductor 2700 162nd Street SW, Building D Lynnwood, WA 98037 Web Sites: 6.1 Phone: 800.669.0557 Facsimile: 425.787.4641 Company Information – http://www.cypress.com Sales – http://www.cypress.com/aboutus/sales_locations.cfm Technical Support – http://www.cypress.com/support/login.