Datasheet

CY8C21634, CY8C21534, CY8C21434
CY8C21334, CY8C21234
Document Number: 38-12025 Rev. AB Page 32 of 53
Figure 14. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 28. 2.7-V AC Characteristics of the I
2
C SDA and SCL Pins (Fast Mode not Supported)
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
F
SCLI2C
SCL clock frequency 0 100 ––kHz
T
HDSTAI2C
Hold time (repeated) start condition. After this
period, the first clock pulse is generated.
4.0 – – –µs
T
LOWI2C
Low period of the SCL clock 4.7 – – –µs
T
HIGHI2C
High period of the SCL clock 4.0 – – –µs
T
SUSTAI2C
Setup time for a repeated start condition 4.7 – – –µs
T
HDDATI2C
Data hold time 0 – – –µs
T
SUDATI2C
Data setup time 250 – – –ns
T
SUSTOI2C
Setup time for stop condition 4.0 – – –µs
T
BUFI2C
Bus free time between a stop and start
condition
4.7 –––µs
T
SPI2C
Pulse width of spikes are suppressed by the
input filter.
– –––ns
I2C_SDA
I2C_SCL
S
Sr
SP
T
BUFI2C
T
SPI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
START Condition Repeated START Condition
STOP Condition