Datasheet

CY8C21634, CY8C21534, CY8C21434
CY8C21334, CY8C21234
Document Number: 38-12025 Rev. AB Page 10 of 53
28-pin Part Pinout
Figure 5. CY8C21534 28-pin PSoC Device
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
V
SS
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
V
SS
V
DD
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Pin Definitions
CY8C21534 28-pin SSOP
Pin No.
Type
Name Description
Digital Analog
1 I/O I, M P0[7] Analog column mux input
2 I/O I, M P0[5] Analog column mux input and column output
3 I/O I, M P0[3] Analog column mux input and column output, integrating input
4 I/O I, M P0[1] Analog column mux input, integrating input
5 I/O M P2[7]
6 I/O M P2[5]
7 I/O I, M P2[3] Direct switched capacitor block input
8 I/O I, M P2[1] Direct switched capacitor block input
9 Power V
SS
Ground connection
10 I/O M P1[7] I
2
C SCL
11 I/O M P1[5] I
2
C SDA
12 I/O M P1[3]
13 I/O M P1[1] I
2
C SCL, ISSP-SCLK
[11]
14 Power V
SS
Ground connection
15 I/O M P1[0] I
2
C SDA, ISSP-SDATA
[11]
16 I/O M P1[2]
17 I/O M P1[4] Optional external clock input (EXTCLK)
18 I/O M P1[6]
19 Input XRES Active high external reset with internal pull-down
20 I/O I, M P2[0] Direct switched capacitor block input
21 I/O I, M P2[2] Direct switched capacitor block input
22 I/O M P2[4]
23 I/O M P2[6]
24 I/O I, M P0[0] Analog column mux input
25 I/O I, M P0[2] Analog column mux input
26 I/O I, M P0[4] Analog column mux input
27 I/O I, M P0[6] Analog column mux input
28 Power V
DD
Supply voltage
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
Note
11. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.