Datasheet

ManualsBrandsCypress Semiconductor ManualsComputer equipmentCY8C21234

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

PSoC

Programmable System-on-Chip™

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-12025 Rev. AB Revised July 25, 2013

PSoC

Programmable System-on-Chip™

Features

■ Powerful Harvard-architecture processor

❐ M8C processor speeds up to 24 MHz

❐ Low power at high speed

❐ Operating voltage: 2.4 V to 5.25 V

❐ Operating voltages down to 1.0 V using on-chip switch mode

pump (SMP)

❐ Industrial temperature range: –40 °C to +85 °C

■ Advanced peripherals (PSoC

blocks)

❐ Four analog Type E PSoC blocks provide:

• Two comparators with digital-to-analog converter (DAC)

references

• Single or dual 10-bit 28 channel analog-to-digital

converters (ADC)

❐ Four digital PSoC blocks provide:

• 8- to 32-bit timers, counters, and pulse width modulators

(PWMs)

• Cyclical redundancy check (CRC) and pseudo random

sequence (PRS) modules

• Full-duplex universal asynchronous receiver transmitter

(UART), serial peripheral interface (SPI) master or slave

• Connectable to all general purpose I/O (GPIO) pins

❐ Complex peripherals by combining blocks

■ Flexible on-chip memory

❐ 8 KB flash program storage 50,000 erase/write cycles

❐ 512 bytes static random access memory (SRAM) data

storage

❐ In-system serial programming (ISSP)

❐ Partial flash updates

❐ Flexible protection modes

❐ EEPROM emulation in flash

■ Complete development tools

❐ Free development software (PSoC Designer™)

❐ Full-featured, in-circuit emulator (ICE) and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128-KB trace memory

■ Precision, programmable clocking

❐ Internal ±2.5% 24- / 48-MHz main oscillator

[1]

❐ Internal oscillator for watchdog and sleep

■ Programmable pin configurations

❐ 25-mA sink, 10-mA source on all GPIOs

❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes

on all GPIOs

❐ Up to eight analog inputs on GPIOs

❐ Configurable interrupt on all GPIOs

■ Versatile analog mux

❐ Common internal analog bus

❐ Simultaneous connection of I/O combinations

❐ Capacitive sensing application capability

■ Additional system resources

❐ I

[2]

master, slave, and multi-master to 400 kHz

❐ Watchdog and sleep timers

❐ User-configurable low-voltage detection (LVD)

❐ Integrated supervisory circuit

❐ On-chip precision voltage reference

Logic Block Diagram

Errata: For information on silicon errata, see “Errata” on page 48. Details include trigger conditions, devices affected, and proposed workaround.

Notes

1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

2. Errata:The I

C block exhibits occasional data and bus corruption errors when the I

C master initiates transactions while the device is transitioning in to or out of sleep

mode.

Summary of content (53 pages)

PAGE 1
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 PSoC® Programmable System-on-Chip™ PSoC® Programmable System-on-Chip™ Features ■ ■ ❐ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ Low power at high speed ❐ Operating voltage: 2.4 V to 5.25 V ❐ Operating voltages down to 1.
PAGE 2
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Contents PSoC Functional Overview .............................................. 3 The PSoC Core ........................................................... 3 The Digital System ...................................................... 3 The Analog System ..................................................... 4 Additional System Resources ..................................... 4 PSoC Device Characteristics ......................................
PAGE 3
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 The Analog System The Analog Multiplexer System The analog system consists of four configurable blocks that allow for the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are: The analog mux bus can connect to every GPIO pin.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted in Table 1. Table 1.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Pin Information The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O. 16-pin Part Pinout Figure 3.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 20-pin Part Pinout Figure 4. CY8C21334 20-pin PSoC Device A, I, M, P0[7] 1 20 VDD A, I, M, P0[5] 2 19 P0[6], A, I, M A, I, M, P0[3] 3 18 P0[4], A, I, M A, I, M, P0[1] 4 17 P0[2], A, I, M VSS 5 16 P0[0], A, I, M M, I2C SCL, P1[7] 6 15 XRES M, I2C SDA, P1[5] 7 14 P1[6], M M, P1[3] 8 13 P1[4], EXTCLK, M M, I2C SCL, P1[1] 9 12 P1[2], M VSS 10 11 P1[0], I2C SDA, M SSOP Pin Definitions CY8C21334 20-pin SSOP Pin No.
PAGE 10
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 28-pin Part Pinout Figure 5.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 32-pin Part Pinout Figure 6. CY8C21434 32-pin PSoC Device Figure 9. CY8C21634 32-pin Sawn PSoC Device Sawn M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] Document Number: 38-12025 Rev.
PAGE 12
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Pin Definitions CY8C21434/CY8C21634 32-pin QFN [12] Pin No.
PAGE 13
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 56-pin Part Pinout The 56-pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Figure 10.
PAGE 14
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Pin Definitions (continued) CY8C21001 56-pin SSOP Type Pin No.
PAGE 15
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Register Reference This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, see the PSoC Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in Table 2. Table 2.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Table 3.
PAGE 17
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Table 4.
PAGE 18
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Absolute Maximum Ratings Symbol TSTG Description Storage temperature TBAKETEMP Bake temperature tBAKETIME Bake time TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Electrostatic discharge voltage Latch-up current Min –55 Typ 25 Max +100 Units °C – 125 °C See package label –40 –0.5 VSS – 0.5 VSS – 0.
PAGE 19
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up-to-date electrical specifications, visit the Cypress web site at http://www.cypress.com. Specifications are valid for –40 C  TA  85 C and TJ  100 C as specified, except where noted. Refer to Table 16 on page 25 for the electrical specifications for the IMO using SLIMO mode. Figure 11. Voltage versus CPU Frequency Figure 14.
PAGE 20
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 DC General-Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 6. 5-V and 3.
PAGE 21
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 8.
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CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 DC Switch Mode Pump Specifications Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Figure 12.
PAGE 23
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Table 11. DC Switch Mode Pump (SMP) Specifications (continued) Symbol Description E2 Efficiency FPUMP DCPUMP Switching frequency Switching duty cycle Min 35 Typ 80 Max – Units % – – 1.3 50 – – MHz % Notes For I load = 1mA, VPUMP = 2.55 V, VBAT = 1.
PAGE 24
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 DC Programming Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 14.
PAGE 25
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 AC Electrical Characteristics AC Chip-Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 16. 5-V and 3.
PAGE 26
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Table 17. 2.7-V AC Chip-Level Specifications Symbol FIMO12 [28] Description IMO frequency for 12 MHz Min 11.04 Typ 120 Max 12.96 [29, 30] Units MHz FIMO6 [28] IMO frequency for 6 MHz 5.52 6 6.48 [29, 30] MHz FCPU1 CPU frequency (2.7 V nominal) 0.093 3 3.15[29] MHz FBLK27 Digital PSoC block frequency (2.7 V nominal) 0 12 12.
PAGE 27
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 AC General Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 18. 5-V and 3.
PAGE 28
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 21. 5-V and 3.
PAGE 29
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Table 22. 2.7-V AC Digital Block Specifications Function Description All functions Block input clock frequency Timer Capture pulse width Input clock frequency, with or without capture Counter Typ Max Units Notes – – 12.7 MHz 2.4 V < VDD < 3.0 V 100[33] – – ns – – 12.7 MHz 100 – – ns Input clock frequency, no enable input – – 12.7 MHz Input clock frequency, enable input – – 12.
PAGE 30
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Table 24. 3.3-V AC External Clock Specifications Min Typ Max Units Notes FOSCEXT Symbol Frequency with CPU clock divide by 1 Description 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements FOSCEXT Frequency with CPU clock divide by 2 or greater 0.186 – 24.
PAGE 31
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 AC Programming Specifications Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, or 3.0 V to 3.6 V and –40 °C  TA  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 26.
PAGE 32
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Table 28. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated.
PAGE 33
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Packaging Information This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 15.
PAGE 34
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Figure 16. 20-pin SSOP (210 Mils) Package Outline, 51-85077 51-85077 *E Figure 17. 28-pin SSOP (210 Mils) Package Outline, 51-85079 51-85079 *E Document Number: 38-12025 Rev.
PAGE 35
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Figure 18. 32-pin QFN (5 × 5 × 1.0 mm) Package Outline, 001-30999 001-30999 *D Important Note For information on the preferred dimensions for mounting QFN packages, see the Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Document Number: 38-12025 Rev.
PAGE 36
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) Package Outline, 001-48913 001-48913 *C Figure 20. 56-pin SSOP (300 Mils) Package Outline, 51-85062 51-85062 *F Document Number: 38-12025 Rev.
PAGE 37
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Thermal Impedances Table 29. Thermal Impedances per Package Typical JA [37] 123 °C/W 117 °C/W 96 °C/W 27 °C/W 22 °C/W 48 °C/W Package 16-pin SOIC 20-pin SSOP 28-pin SSOP 32-pin QFN[38] 5 × 5 mm 0.60 Max 32-pin QFN[38] 5 × 5 mm 1.00 Max 56-pin SSOP Typical JC 55 °C/W 41 °C/W 39 °C/W 15 °C/W 12 °C/W 24 °C/W Solder Reflow Specifications Table 30 shows the solder reflow temperature limits that must not be exceeded. Table 30.
PAGE 38
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C21x34 family. Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler.
PAGE 39
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer CY3207ISSP In-System Serial Programmer (ISSP) The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: The CY3207ISSP is a production programmer.
PAGE 40
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 SRAM (Bytes) Switch Mode Pump Temperature Range Digital Blocks Analog Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin 16-Pin (150-Mil) SOIC CY8C21234-24SXI 8K 512 Yes –40 °C to +85 °C 4 4 12 12[42] 0 No 16-Pin (150-Mil) SOIC (Tape and Reel) CY8C21234-24SXIT 8K 512 Yes –40 °C to +85 °C 4 4 12 12[42] 0 No 20-Pin (210-Mil) SSOP CY8C21334-24PVXI 8K 512 No –40 °C to +85 °C 4 4 16 16[42] 0 Yes [42] 0
PAGE 41
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Ordering Code Definitions CY 8 C 21 xxx -24 xx Package Type: Thermal Rating: PX = PDIP Pb-free C = Commercial SX = SOIC Pb-free I = Industrial PVX = SSOP Pb-free E = Extended LFX/LKX/LTX/LCX/LQX = QFN Pb-free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 38-12025 Rev.
PAGE 42
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Acronyms Table 32 lists the acronyms that are used in this document. Table 32.
PAGE 43
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Document Conventions Units of Measure Table 33 lists the units of measures. Table 33.
PAGE 44
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2.
PAGE 45
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. External Reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state.
PAGE 46
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller.
PAGE 47
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface.
PAGE 48
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Errata This section describes the errata for the PSoC® Programmable System-on-Chip CY8C21234. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
PAGE 49
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 CY8C21234 Errata Summary The following table defines the errata applicability to available CY8C21234 family devices. An "X" indicates that the errata pertains to the selected device. Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description. Items Part Number Silicon Revision Fix Status [1.].
PAGE 50
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Document History Page Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC® Programmable System-on-Chip™ Document Number: 38-12025 Rev. ECN Orig. of Change Submission Date Description of Change ** 227340 HMT See ECN New silicon and document (Revision **). *A 235992 SFV See ECN Updated Overview and Electrical Spec. chapters, along with revisions to the 24-Pin pinout part. Revised the register mapping tables.
PAGE 51
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Document History Page (continued) Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC® Programmable System-on-Chip™ Document Number: 38-12025 Rev. ECN Orig. of Change Submission Date Description of Change *R 2762499 JVY 09/11/2009 Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Modified FIMO6 and TWRITE specifications.
PAGE 52
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Document History Page (continued) Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC® Programmable System-on-Chip™ Document Number: 38-12025 Rev. ECN Orig. of Change Submission Date Description of Change *Z 3902039 VNJ 02/12/2013 Updated Electrical Specifications (Updated AC Electrical Characteristics (Updated AC Chip-Level Specifications (Updated Table 16 (Changed minimum value of FIMO6 parameter from 5.5 MHz to 5.
PAGE 53
CY8C21634, CY8C21534, CY8C21434 CY8C21334, CY8C21234 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.