Specifications

Getting Started with FX2LP™
www.cypress.com Document No. 001-65209 Rev. *B 4
Different variants of FX2LP
FX2LP is available in three different Pb free pin/packages:

56-pin version available in SSOP, QFN, VFBGA
packages.

100-pin version available only in TQFP package.

128-pin version available only in TQFP package.
Table 2 shows the comparison of these three different packages of FX2LP.
Table 2. Comparison of Features of Three Different Packages of FX2LP
Feature 56-pin package 100-pin package 128-pin package
8-bit I/O ports 3 ports (Port A, B, D) 5 ports (Port A, B, C, D, E) 5 ports (port A, B, C, D, E)
I2C bus Available Available Available
UART Not Available. So firmware
debugging through UART is not
possible with this package.
Available Available
GPIF as master

8- or 16-bit GPIF multiplexed onto
Port B and D.

5 non-multiplexed control signals

8- or 16-bit GPIF multiplexed onto
Port B and D.

12 non-multiplexed control signals

Nine GPIF address lines,
multiplexed onto PORTC (eight) and
PORTE (one)

8- or 16-bit GPIF multiplexed onto
Port B and D.

12 non-multiplexed control signals

Nine GPIF address lines,
multiplexed onto PORTC (eight)
and PORTE (one)
Slave FIFO

8- or 16-bit Slave FIFO Interface
multiplexed onto Port B and D.

5 non-multiplexed control
signals and 4 or 5 control
signals multiplexed with Port A.

8- or 16-bit Slave FIFO Interface
multiplexed onto Port B and D.

5 non-multiplexed control signals
and 4 or 5 control signals
multiplexed with Port A.

8- or 16-bit Slave FIFO Interface
multiplexed onto Port B and D.

5 non-multiplexed control signals
and 4 or 5 control signals
multiplexed with Port A.
Other features CY7C68015A and CY7C68016A
have two additional GPIO signals to
provide more flexibility when neither
IFCLK or CLKOUT are needed in the
56-pin package. PE0 (Port E, pin 0)
replaces the IFCLK and PE1
replaces the CLKOUT.
RD# and WR# signals which may be
used as read and write strobes for
PORTC
RD# and WR# signals which may be
used as read and write strobes for
PORTC 16-bit 8051 address bus to
access off chip memory. 8-bit 8051
data bus. Address/data bus control
signals
In the same USB High-speed peripherals family, we have
the following additional devices:

AT2LP: Cypress’s EZ-USB
®
AT2LP™
(CY7C68300C/301C/320C) implements a fixed-
function bridge between one USB port and one or two
ATA- or ATAPI-based mass storage device ports. The
PATA interface on AT2LP enables the use of hard
disk drives (HDD), compact flash, and solid state
drives (SSD) in your design. The AT2LP is perfect for
mass storage type applications and enable quick time
to market without the hassle of custom firmware.
AT2LP supports all ATA/ATAPI-6 compliant mass
storage devices.

NX2LP-Flex: Cypress’s EZ-USB NX2LP-Flex™
(CY7C68033/34) is a fixed-function, low-power
programmable USB to SLC NAND controller. The
flexibility of NX2LP-Flex makes it superior to other
fixed function NAND controller. Its programmability
allows for designers to include special features in the
controller along with support multiple different NAND
devices easily with one single controller. The
hardware ECC engine present in NX2LP-Flex
supports 1-bit error correction and 2-bit error
detection.

SX2: The EZ-USB SX2 (CY7C68001) is a
programmable device designed to work with any
external master, such as standard microprocessors,
DSPs, ASICs, and FPGAs to enable USB 2.0 support
for any peripheral design. SX2 has a built-in USB
transceiver and serial interface engine (SIE), along
with a command decoder to send and receive USB
data. The controller has four endpoints that share a
4-KB FIFO space for maximum flexibility and
throughput. SX2 has three address pins and a
selectable 8- or 16- bit data bus for command and
data input or output.