Specifications

Getting Started with FX2LP™
www.cypress.com Document No. 001-65209 Rev. *B 3
Introduction to FX2LP
EZ-USB FX2LP (CY7C68013A/14A/15A/16A) is a programmable, low-power USB 2.0 USB peripheral controller. The FX2LP
chipset integrates the USB 2.0 transceiver, serial interface engine (SIE), an enhanced 8051 microcontroller, and a
programmable peripheral interface in a single chip. Using this, you can create a wide range of cost-effective solutions with
superior time-to-market. The low-power consumption enables you to create both bus-powered and self-powered applications.
Figure 2. FX2LP Block Diagram
Features of FX2LP
USB:

FX2LP has an integrated USB 2.0 transceiver, serial
interface engine (SIE).

4 KB of endpoint memory.

Endpoint type (BULK, INTERRUPT and
ISOCHRONOUS) and Endpoint buffering (double,
triple, quad) are programmable.

Additional programmable (BULK/INTERRUPT)
64 byte endpoint.

7 physical endpoints including the control endpoint.
CPU and memory:

FX2LP has an enhanced 8051 core with two USART,
three counter/timers, and an expanded interrupt
system. The core can work on 48 MHz, 24 MHz, or
12 MHz clock.

16 KB of on-chip code/data RAM.

Program needs to be stored in an external nonvolatile
memory as no flash memory exists in the FX2LP. You
can also download the program from the USB host.
Serial interfaces:

Integrated I
2
C controller, which runs at 100 or
400 kHz.

UART interface.

Up to 40 GPIOs.
Parallel interface:

Has a general-purpose programming interface (GPIF)
with 8/16-bit external data interface. Using GPIF,
FX2LP can directly connect to most parallel
interfaces. GPIF has 9 address lines, 6 control lines
and 6 ready signals. Typically used when FX2LP is a
master on the interface.

Slave FIFO interface – typically used when FX2LP
needs to function as a slave device on the interface.