Specifications
Getting Started with FX2LP™
www.cypress.com Document No. 001-65209 Rev. *B 24
Xilinx Spartan-6 (XC6SLX45-2FGG or XC6SLX150-
2FGG)
32-Mib serial flash (Numonyx M32P25)
128-MiByte DDR2 (Micron MT47H64M16HR)
Small form-factor -- smaller than a credit card at
75 mm x 50 mm x 15.9 mm (2.95" x 1.97" x 0.63")
Self-powered by external DC source
Multi-PLL, multi-output clock generator (Cypress
CY22393).
Third party SDKs
ZTEX provides a SDK which works with FX2LP based
boards and also provides JAVA based APIs to help
development of the host software.
For more details, please visit http://www.ztex.de/firmware-kit/
Related Documentation
Technical Reference Manual
EZ-USB Technical Reference Manual
This document explains the various blocks present in the
FX2LP and also it has description and usage of all
registers. This document is available as part of the DVK
documents.
Application Notes
AN65209 - Getting Started with FX2LP
This application note presents the features and resources
available to speed up the EZ-USB FX2LP.-based design
from concept to production. This document serves as a
starting point for the new user to get familiar with FX2LP. It
also gives an overview of the design resources available
AN1168 - High-speed USB PCB Layout
Recommendations
This application note details guidelines for designing,
controlled-impedance; high-speed USB printed circuit
boards to comply with the USB specification. This note is
applicable to all Cypress high-speed USB solutions. Some
Cypress high-speed USB chips have separate application
notes that address chip-specific PCB design guidelines
AN15456 - Guide to Successful EZ-USB
®
FX2LP™
and EZ-USB FX1™ Hardware Design and Debug
This application note outlines a process that isolates many
of the most likely causes of EZ-USB FX2LP, and EZ-USB
FX1 hardware problems. It also facilitates the process of
catching potential problems before building a board and
assists in the debugging when getting a board up and
running.
AN064 - EZ-USB FX2LP/AT2LP. Reset and Power
Considerations
Many designers have had difficulty with the reset and
power needs of the FX2LP and the USB specification.
This Application Note addresses the main areas where
USB and FX2LP designs have special needs. Both these
chips (FX2LP, AT2LP) have similar power and reset
needs. This application note refers to the FX2LP, but is
also applicable to AT2LP.
AN5078 - EZ-USB Hardware - Design considerations
for EEPROM usage
EZ-USB downloads firmware automatically into the on-
chip RAM from the EEPROM connected to it. The purpose
of this application note is to present recommended design
guidelines for assuring the data integrity of serial
EEPROM devices when used in EZ-USB designs.
AN50963 - Firmware Download Methods to
FX1/FX2LP
This application note discusses the various methods to
download firmware in to FX1/FX2LP.
AN66806 - EZ-USB
®
FX2LP™ GPIF Design Guide
This application note helps you in teaching the steps to
develop GPIF waveforms using the GPIF designer.
AN61345 - Implementing an FX2LP™- FPGA
Interface
This application note provides a sample project to
interface an FX2LP™ with FPGA. An FX2LP™-FPGA
interface is implemented to add High-Speed USB
connectivity for FPGA based applications, such as data
acquisition, industrial control and monitoring, and image
processing. The FX2LP acts in Slave-FIFO mode and the
FPGA acts as the master. This Application Note also gives
a sample FX2LP firmware for Slave-FIFO implementation
and a sample VHDL and Verilog project for FPGA
implementation.
AN58009 - Serial (UART) Port Debugging of
FX1/FX2LP Firmware
This application note describes the code needed in the
FX2LP firmware for serial debugging. This code enables
the developer to print debug messages and real time
values of the required variables in the HyperTerminal of
the PC or capture it in a file using the UART engine in
FX2LP.
AN42499 - Setting Up, Using, and Troubleshooting
the Keil Debugger Environment
This application note is a step-by-step beginner's guide to
using the Keil Debugger. This guide covers the serial
cable connection from PC to SIO-1/0, the monitor code
download, and required project settings. Additionally, the
guidelines to start and stop a debug session, set