User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 9 of 71
2.9 Reset and Wakeup
2.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP when asserted. This
pin has hysteresis and is active LOW. When a crystal is used with
the CY7C680xxA, the reset period must enable stabilization of
the crystal and the PLL. This reset period must be approximately
5 ms after VCC reaches 3.0 V. If the crystal input pin is driven by
a clock signal, the internal PLL stabilizes in 200 s after VCC has
reached 3.0 V.
[4]
Figure 2-2 on page 9 shows a power-on reset condition and a
reset applied during operation. A power-on reset is defined as
the time reset that is asserted while power is being applied to the
circuit. A powered reset is when the FX2LP is powered on and
operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power-on reset implementation. For more
information about reset implementation for the FX2 family of
products, visit http://www.cypress.com.
2.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts after the PLL stabilizes, and the 8051 receives a wakeup
interrupt. This applies irrespective of whether FX2LP is
connected to the USB.
The FX2LP exits the power-down (USB suspend) state by using
one of the following methods:
■ USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
■ External logic asserts the WAKEUP pin
■ External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a
general-purpose I/O pin. This enables a simple external R-C
network to be used as a periodic wakeup source. WAKEUP is by
default active LOW.
Figure 2-2. Reset Timing Plots
V
IL
0V
3.3V
3.0V
T
RESET
VCC
RESET#
Power on Reset
T
RESET
VCC
RESET#
V
IL
Powered Reset
3.3V
0V
Table 2-1. Reset Timing Values
Condition T
RESET
Power-on reset with crystal 5 ms
Power-on reset with external
clock
200 s + clock stability time
Powered reset 200 s
Note
4. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 s.