User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 49 of 71
9.10 Slave FIFO Asynchronous Write
Figure 9-10. Slave FIFO Asynchronous Write Timing Diagram
[24]
9.11 Slave FIFO Synchronous Packet End Strobe
Figure 9-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram
[24]
DATA
t
SFD
t
FDH
FLAGS
t
XFD
SLWR/SLCS#
t
WRpwh
t
WRpwl
SLWR
Table 24. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
[27]
Parameter Description Min Max Unit
t
WRpwl
SLWR pulse LOW 50 – ns
t
WRpwh
SLWR pulse HIGH 70 – ns
t
SFD
SLWR to FIFO DATA setup time 10 – ns
t
FDH
FIFO DATA to SLWR hold time 10 – ns
t
XFD
SLWR to FLAGS output propagation delay – 70 ns
FLAGS
t
XFLG
IFCLK
PKTEND
t
SPE
t
PEH
Table 25. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
[25]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period 20.83 – ns
t
SPE
PKTEND to clock setup time 14.6 – ns
t
PEH
Clock to PKTEND hold time 0 – ns
t
XFLG
Clock to FLAGS output propagation delay – 9.5 ns
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
[25]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period 20.83 200 ns
t
SPE
PKTEND to clock setup time 8.6 – ns
t
PEH
Clock to PKTEND hold time 2.5 – ns
t
XFLG
Clock to FLAGS output propagation delay – 13.5 ns