User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 47 of 71
9.8 Slave FIFO Asynchronous Read
Figure 9-8. Slave FIFO Asynchronous Read Timing Diagram
[24]
Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
[25]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period 20.83 200 ns
t
SRD
SLRD to clock setup time 12.7 – ns
t
RDH
Clock to SLRD hold time 3.7 – ns
t
OEon
SLOE turn on to FIFO data valid – 10.5 ns
t
OEoff
SLOE turn off to FIFO data hold – 10.5 ns
t
XFLG
Clock to FLAGS output propagation delay – 13.5 ns
t
XFD
Clock to FIFO data output propagation delay – 15 ns
SLRD
FLAGS
t
RDpwl
t
RDpwh
SLOE
t
XFLG
t
XFD
DATA
t
OEon
t
OEoff
N+1
N
Table 21. Slave FIFO Asynchronous Read Parameters
[27]
Parameter Description Min Max Unit
t
RDpwl
SLRD pulse width LOW 50 – ns
t
RDpwh
SLRD pulse width HIGH 50 – ns
t
XFLG
SLRD to FLAGS output propagation delay – 70 ns
t
XFD
SLRD to FIFO data output propagation delay – 15 ns
t
OEon
SLOE turn-on to FIFO data valid – 10.5 ns
t
OEoff
SLOE turn-off to FIFO data hold – 10.5 ns
Note
27. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.