User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 46 of 71
9.1 Slave FIFO Synchronous Read
Figure 9-7. Slave FIFO Synchronous Read Timing Diagram
[24]
IFCLK
SLRD
FLAGS
SLOE
t
SRD
t
RDH
t
OEon
t
XFD
t
XFLG
DATA
t
IFCLK
N+1
t
OEoff
N
Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
[25]
Parameter Description Min Max
Typ
Unit
Min Max
t
IFCLK
IFCLK period 20.83 – – – ns
t
SRD
SLRD to clock setup time 18.7 – – – ns
t
RDH
Clock to SLRD hold time 0 – – – ns
t
OEon
SLOE turn on to FIFO data valid – 10.5 – – ns
t
OEoff
SLOE turn off to FIFO data hold – 10.5 – – ns
t
XFLG
Clock to FLAGS output propagation delay – 9.5 – – ns
t
XFD
Clock to FIFO data output propagation delay – 11 – – ns
t
IFCLKR
IFCLK rise time – – – 900 ps
t
IFCLKF
IFCLK fall time – – – 900 ps
t
IFCLKOD
IFCLK output duty cycle – – 49 51 %
t
IFCLKJ
IFCLK jitter peak to peak – – – 300 ps