User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 45 of 71
9.6 GPIF Synchronous Signals
Figure 9-6. GPIF Synchronous Signals Timing Diagram
[24]
DATA(output)
t
XGD
IFCLK
RDY
X
DATA(input)
valid
t
SRY
t
RYH
t
IFCLK
t
SGD
CTL
X
t
XCTL
t
DAH
N
N+1
GPIFADR[8:0]
t
SGA
Table 17. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
[24, 25]
Parameter Description Min Max
Typ
Unit
Min Max
t
IFCLK
IFCLK Period 20.83 – – – ns
t
SRY
RDY
X
to clock setup time 8.9 – – – ns
t
RYH
Clock to RDY
X
0 –––ns
t
SGD
GPIF data to clock setup time 9.2 – – – ns
t
DAH
GPIF data hold time 0 – – – ns
t
SGA
Clock to GPIF address propagation delay – 7.5 – – ns
t
XGD
Clock to GPIF data output propagation delay – 11 – – ns
t
XCTL
Clock to CTL
X
output propagation delay – 6.7 – – ns
t
IFCLKR
IFCLK rise time – – – 900 ps
t
IFCLKF
IFCLK fall time – – – 900 ps
t
IFCLKOD
IFCLK output duty cycle – – 49 51 %
t
IFCLKJ
IFCLK jitter peak to peak – – – 300 ps
Table 18. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
[25]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period
[26]
20.83 200 ns
t
SRY
RDY
X
to clock setup time 2.9 – ns
t
RYH
Clock to RDY
X
3.7 – ns
t
SGD
GPIF data to clock setup time 3.2 – ns
t
DAH
GPIF data hold time 4.5 – ns
t
SGA
Clock to GPIF address propagation delay – 11.5 ns
t
XGD
Clock to GPIF data output propagation delay – 15 ns
t
XCTL
Clock to CTL
X
output propagation delay – 10.7 ns
Notes
24. Dashed lines denote signals with programmable polarity.
25. GPIF asynchronous RDY
x
signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
26. IFCLK must not exceed 48 MHz.