User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 43 of 71
9.4 Data Memory Write
[23]
Figure 9-3. Data Memory Write Timing Diagram
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on
the stretch value.
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
t
STBL
t
STBH
data out
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
data out
Stretch = 1
t
ON1
t
SCSL
t
AV
CS#
t
ON1
CS#
Table 16. Data Memory Write Parameters
Parameter Description Min Max Unit Notes
t
AV
Delay from clock to valid address 0 10.7 ns –
t
STBL
Clock to WR pulse LOW 0 11.2 ns –
t
STBH
Clock to WR pulse HIGH 0 11.2 ns –
t
SCSL
Clock to CS pulse LOW – 13.0 ns –
t
ON1
Clock to data turn-on 0 13.1 ns –
t
OFF1
Clock to data hold time 0 13.1 ns –
Note
23. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including
typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.