User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 41 of 71
9. AC Electrical Characteristics
9.1 USB Transceiver
USB 2.0 compliant in Full-Speed and Hi-Speed modes.
9.2 Program Memory Read
Figure 9-1. Program Memory Read Timing Diagram
t
CL
t
DH
t
SOEL
t
SCSL
PSEN#
D[7..0]
OE#
A[15..0]
CS#
t
STBL
data in
t
ACC1
t
AV
t
STBH
t
AV
CLKOUT
[19]
[20]
Table 14. Program Memory Read Parameters
Parameter Description Min Typ Max Unit Notes
t
CL
1/CLKOUT frequency – 20.83 – ns 48 MHz
– 41.66 – ns 24 MHz
– 83.2 – ns 12 MHz
t
AV
Delay from clock to valid address 0 – 10.7 ns –
t
STBL
Clock to PSEN LOW 0 – 8 ns –
t
STBH
Clock to PSEN HIGH 0 – 8 ns –
t
SOEL
Clock to OE LOW – – 11.1 ns –
t
SCSL
Clock to CS LOW – – 13 ns –
t
DSU
Data setup to clock 9.6 – – ns –
t
DH
Data hold time 0 – – ns –
Notes
19. CLKOUT is shown with positive polarity.
20. t
ACC1
is computed from these parameters as follows:
t
ACC1
(24 MHz) = 3*t
CL
– t
AV
– t
DSU
= 106 ns.
t
ACC1
(48 MHz) = 3*t
CL
– t
AV
– t
DSU
= 43 ns.