User guide
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 30 of 71
30 24 – – – T1 Input N/A N/A T1 is the active HIGH T1 signal for 8051 Timer1,
which provides the input to Timer1 when C/T1 is 1.
When C/T1 is 0, Timer1 does not use this bit.
29 23 – – – T0 Input N/A N/A T0 is the active HIGH T0 signal for 8051 Timer0,
which provides the input to Timer0 when C/T0 is 1.
When C/T0 is 0, Timer0 does not use this bit.
53 43 – – – RXD1 Input N/A N/A RXD1is an active HIGH input signal for 8051
UART1, which provides data to the UART in all
modes.
52 42 – – – TXD1 Output H L TXD1is an active HIGH output pin from 8051
UART1, which provides the output clock in sync
mode, and the output data in async mode.
51 41 – – – RXD0 Input N/A N/A RXD0 is the active HIGH RXD0 input to 8051
UART0, which provides data to the UART in all
modes.
50 40 – – – TXD0 Output H L TXD0 is the active HIGH TXD0 output from 8051
UART0, which provides the output clock in sync
mode, and the output data in async mode.
42 – – – CS# Output H H CS# is the active LOW chip select for external
memory.
41 32 – – – WR# Output H H WR# is the active LOW write strobe output for
external memory.
40 31 – – – RD# Output H H RD# is the active LOW read strobe output for
external memory.
38 – – – OE# Output H H OE# is the active LOW output enable for external
memory.
33 27 21 14 2H Reserved Input N/A N/A Reserved. Connect to ground.
101 79 51 44 7B WAKEUP Input N/A N/A USB Wakeup. If the 8051 is in suspend, asserting
this pin starts up the oscillator and interrupts the
8051 to enable it to exit the suspend mode. Holding
WAKEUP asserted inhibits the EZ-USB chip from
suspending. This pin has programmable polarity
(WAKEUP.4).
36 29 22 15 3F SCL OD Z Z
(if
booting
is done)
Clock for the I
2
C interface. Connect to VCC with a
2.2-k resistor, even if no I
2
C peripheral is attached.
37 30 23 16 3G SDA OD Z Z
(if
booting
is done)
Data for I
2
C compatible interface. Connect to VCC
with a 2.2-k resistor, even if no I
2
C compatible
peripheral is attached.
2 1 6 55 5A VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
26 20 18 11 1G VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
43 33 24 17 7E VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
48 38 – – – VCC Power N/A N/A VCC. Connect to 3.3-V power source.
64 49 34 27 8E VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
68 53 – – – VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
81 66 39 32 5C VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
Table 10. FX2LP Pin Descriptions
[11]
(continued)
128
TQFP
100
TQFP
56
SSOP
56
QFN
56
VFBGA
Name Type Default Reset
[12]
Description