User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 3 of 71
Cypress’s EZ-USB
®
FX2LP (CY7C68013A/14A) is a
low-power version of the EZ-USB FX2(CY7C68013), which is
a highly integrated, low-power USB 2.0 microcontroller. By
integrating the USB 2.0 transceiver, serial interface engine (SIE),
enhanced 8051 microcontroller, and a programmable peripheral
interface in a single chip, Cypress has created a cost-effective
solution that provides superior time-to-market advantages with
low power to enable bus-powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second (the maximum allowable
USB 2.0 bandwidth), while still using a low-cost 8051
microcontroller in a package as small as a 56 VFBGA (5 mm x
5 mm). Because it incorporates the USB 2.0 transceiver, the
FX2LP is more economical, providing a smaller-footprint solution
than a USB 2.0 SIE or external transceiver implementations.
With EZ-USB FX2LP, the Cypress Smart SIE handles most of
the USB 1.1 and 2.0 protocol in hardware, freeing the embedded
microcontroller for application-specific functions and decreasing
the development time to ensure USB compatibility.
The general programmable interface (GPIF) and Master/Slave
Endpoint FIFO (8-bit or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as
ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form, and function
compatible with the 56-, 100-, and 128-pin FX2.
Five packages are defined for the family: 56 VFBGA, 56 SSOP,
56 QFN, 100 TQFP, and 128 TQFP.
Address (16)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
VCC
1.5k
D+
D–
Address (16) / Data Bus (8)
FX2LP
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full speed and
Additional I/Os (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
Data (8)
24 MHz
Ext. XTAL
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Up to 96 MBytes/s
burst rate
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Abundant I/O
including two USARTs
High-performance micro
using standard tools
with lower-power options
Master
connected for
full speed
ECC
XCVR
high speed
Logic Block Diagram