User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 28 of 71
110 88 – – – PE2 or
T2OUT
I/O/Z I
(PE2)
Z
(PE2)
Multiplexed pin whose function is selected by the
PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active HIGH output signal from 8051
Timer2. T2OUT is active (HIGH) for one clock cycle
when Timer/Counter 2 overflows.
111 89 – – – PE3 or
RXD0OUT
I/O/Z I
(PE3)
Z
(PE3)
Multiplexed pin whose function is selected by the
PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active HIGH signal from 8051
UART0. If RXD0OUT is selected and UART0 is in
Mode 0, this pin provides the output data for UART0
only when it is in sync mode. Otherwise it is a 1.
112 90 – – – PE4 or
RXD1OUT
I/O/Z I
(PE4)
Z
(PE4)
Multiplexed pin whose function is selected by the
PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051
UART1. When RXD1OUT is selected and UART1 is
in Mode 0, this pin provides the output data for
UART1 only when it is in sync mode. In Modes 1, 2,
and 3, this pin is HIGH.
113 91 – – – PE5 or
INT6
I/O/Z I
(PE5)
Z
(PE5)
Multiplexed pin whose function is selected by the
PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal.
The INT6 pin is edge-sensitive, active HIGH.
114 92 – – – PE6 or
T2EX
I/O/Z I
(PE6)
Z
(PE6)
Multiplexed pin whose function is selected by the
PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active HIGH input signal to the 8051
Timer2. T2EX reloads timer 2 on its falling edge.
T2EX is active only if the EXEN2 bit is set in T2CON.
115 93 – – – PE7 or
GPIFADR8
I/O/Z I
(PE7)
Z
(PE7)
Multiplexed pin whose function is selected by the
PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
4 3 8 1 1A RDY0 or
SLRD
Input N/A N/A Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD
is the input-only read strobe with program-
mable polarity (FIFOPINPOLAR.3) for the slave
FIFOs connected to FD[7..0] or FD[15..0].
5 4 9 2 1B RDY1 or
SLWR
Input N/A N/A Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with program-
mable polarity (FIFOPINPOLAR.2) for the slave
FIFOs connected to FD[7..0] or FD[15..0].
6 5 – – – RDY2 Input N/A N/A RDY2 is a GPIF input signal.
7 6 – – – RDY3 Input N/A N/A RDY3 is a GPIF input signal.
8 7 – – – RDY4 Input N/A N/A RDY4 is a GPIF input signal.
Table 10. FX2LP Pin Descriptions
[11]
(continued)
128
TQFP
100
TQFP
56
SSOP
56
QFN
56
VFBGA
Name Type Default Reset
[12]
Description