User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 27 of 71
PORT D
102 80 52 45 8A PD0 or
FD[8]
I/O/Z I
(PD0)
Z
(PD0)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
103 81 53 46 7A PD1 or
FD[9]
I/O/Z I
(PD1)
Z
(PD1)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
104 82 54 47 6B PD2 or
FD[10]
I/O/Z I
(PD2)
Z
(PD2)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
105 83 55 48 6A PD3 or
FD[11]
I/O/Z I
(PD3)
Z
(PD3)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
121 95 56 49 3B PD4 or
FD[12]
I/O/Z I
(PD4)
Z
(PD4)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
122 96 1 50 3A PD5 or
FD[13]
I/O/Z I
(PD5)
Z
(PD5)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
123 97 2 51 3C PD6 or
FD[14]
I/O/Z I
(PD6)
Z
(PD6)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
124 98 3 52 2A PD7 or
FD[15]
I/O/Z I
(PD7)
Z
(PD7)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Port E
108 86 – – – PE0 or
T0OUT
I/O/Z I
(PE0)
Z
(PE0)
Multiplexed pin whose function is selected by the
PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051
Timer-counter0. T0OUT outputs a high level for one
CLKOUT clock cycle when Timer0 overflows. If
Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte
timer/counter overflows.
109 87 – – – PE1 or
T1OUT
I/O/Z I
(PE1)
Z
(PE1)
Multiplexed pin whose function is selected by the
PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active HIGH signal from 8051
Timer-counter1. T1OUT outputs a high level for one
CLKOUT clock cycle when Timer1 overflows. If
Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte
timer/counter overflows.
Table 10. FX2LP Pin Descriptions
[11]
(continued)
128
TQFP
100
TQFP
56
SSOP
56
QFN
56
VFBGA
Name Type Default Reset
[12]
Description