User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 26 of 71
47 37 28 21 4G PB3 or
FD[3]
I/O/Z I
(PB3)
Z
(PB3)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
54 44 29 22 5H PB4 or
FD[4]
I/O/Z I
(PB4)
Z
(PB4)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
55 45 30 23 5G PB5 or
FD[5]
I/O/Z I
(PB5)
Z
(PB5)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
56 46 31 24 5F PB6 or
FD[6]
I/O/Z I
(PB6)
Z
(PB6)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
57 47 32 25 6H PB7 or
FD[7]
I/O/Z I
(PB7)
Z
(PB7)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
PORT C
72 57 – – – PC0 or
GPIFADR0
I/O/Z I
(PC0)
Z
(PC0)
Multiplexed pin whose function is selected by
PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73 58 – – – PC1 or
GPIFADR1
I/O/Z I
(PC1)
Z
(PC1)
Multiplexed pin whose function is selected by
PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
74 59 – – – PC2 or
GPIFADR2
I/O/Z I
(PC2)
Z
(PC2)
Multiplexed pin whose function is selected by
PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
75 60 – – – PC3 or
GPIFADR3
I/O/Z I
(PC3)
Z
(PC3)
Multiplexed pin whose function is selected by
PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
76 61 – – – PC4 or
GPIFADR4
I/O/Z I
(PC4)
Z
(PC4)
Multiplexed pin whose function is selected by
PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
77 62 – – – PC5 or
GPIFADR5
I/O/Z I
(PC5)
Z
(PC5)
Multiplexed pin whose function is selected by
PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
78 63 – – – PC6 or
GPIFADR6
I/O/Z I
(PC6)
Z
(PC6)
Multiplexed pin whose function is selected by
PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
79 64 – – – PC7 or
GPIFADR7
I/O/Z I
(PC7)
Z
(PC7)
Multiplexed pin whose function is selected by
PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
Table 10. FX2LP Pin Descriptions
[11]
(continued)
128
TQFP
100
TQFP
56
SSOP
56
QFN
56
VFBGA
Name Type Default Reset
[12]
Description