User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 24 of 71
34 28 – – BKPT Output L L Breakpoint. This pin goes active (HIGH) when the
8051 address bus matches the BPADDRH/L
registers and breakpoints are enabled in the
BREAKPT register (BPEN = 1). If the BPPULSE bit
in the BREAKPT register is HIGH, this signal pulses
HIGH for eight 12-/24-/48-MHz clocks. If the
BPPULSE bit is LOW, the signal remains HIGH until
the 8051 clears the BREAK bit (by writing 1 to it) in
the BREAKPT register.
99 77 49 42 8B RESET# Input N/A N/A Active LOW Reset. Resets the entire chip. See
section 2.9 ”Reset and Wakeup” on page 9 for more
details.
35 – – – – EA Input N/A N/A External Access. This pin determines where the
8051 fetches code between addresses 0x0000 and
0x3FFF. If EA = 0 the 8051 fetches this code from
its internal RAM. IF EA = 1 the 8051 fetches this
code from external memory.
12 11 12 5 1C XTALIN Input N/A N/A Crystal Input. Connect this signal to a 24-MHz
parallel-resonant, fundamental mode crystal and
load capacitor to GND.
It is also correct to drive XTALIN with an external
24-MHz square wave derived from another clock
source. When driving from an external source, the
driving signal should be a 3.3-V square wave.
11 10 11 4 2C XTALOUT Output N/A N/A Crystal Output. Connect this signal to a 24-MHz
parallel-resonant, fundamental mode crystal and
load capacitor to GND.
If an external clock is used to drive XTALIN, leave
this pin open.
1 100 5 54 2B CLKOUT on
CY7C68013
A
and
CY7C68014
A
-----------------
-
PE1 on
CY7C68015
A and
CY7C68016
A
O/Z
----------
-
I/O/Z
12 MHz
----------
I
Clock
Driven
----------
Z
CLKOUT: 12-, 24- or 48-MHz clock, phase-locked
to the 24-MHz input clock. The 8051 defaults to
12-MHz operation. The 8051 may three-state this
output by setting CPUCS.1 = 1.
-------------------------------------------------------------------
-----PE1 is a bidirectional I/O port pin.
Port A
82 67 40 33 8G PA0 or
INT0#
I/O/Z I
(PA0)
Z
(PA0)
Multiplexed pin whose function is selected by
PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input
signal, which is either edge-triggered (IT0 = 1) or
level-triggered (IT0 = 0).
83 68 41 34 6G PA1 or
INT1#
I/O/Z I
(PA1)
Z
(PA1)
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input
signal, which is either edge-triggered (IT1 = 1) or
level-triggered (IT1 = 0).
Table 10. FX2LP Pin Descriptions
[11]
(continued)
128
TQFP
100
TQFP
56
SSOP
56
QFN
56
VFBGA
Name Type Default Reset
[12]
Description