User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 12 of 71
2.12 Endpoint RAM
2.12.1 Size
3 × 64 bytes (Endpoints 0 and 1)
8 × 512 bytes (Endpoints 2, 4, 6, 8)
2.12.2 Organization
EP0
Bidirectional endpoint zero, 64-byte buffer
EP1IN, EP1OUT
64 byte buffers, bulk or interrupt
EP2, 4, 6, 8
Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered; EP2 and 6 can be either double,
triple, or quad buffered. For Hi-Speed endpoint configuration
options, see Figure 2-5.
2.12.3 Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
2.12.4 Endpoint Configurations (Hi-Speed Mode)
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT.
The endpoint buffers can be configured in any 1 of the 12
configurations shown in the vertical columns. When operating in
the Full-Speed BULK mode, only the first 64 bytes of each buffer
are used. For example, in Hi-Speed mode, the max packet size
is 512 bytes, but in Full-Speed mode, it is 64 bytes. Even though
a buffer is configured to a 512-byte buffer, in Full-Speed mode,
only the first 64 bytes are used. The unused endpoint buffer
space is not available for other operations. An example endpoint
configuration is the EP2–1024 double-buffered; EP6–512
quad-buffered (column 8).
Figure 2-5. Endpoint Configuration