User guide

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Number: 38-08032 Rev. *X Page 10 of 71
2.10 Program/Data RAM
2.10.1 SizeThe FX2LP has 16 KB of internal program/data RAM,
where PSEN#/RD# signals are internally ORed to enable
the 8051 to access it as both program and data memory.
No USB control registers appears in this space.
Two memory maps are shown in the following diagrams:
Figure 2-3 on page 10 shows the Internal Code Memory, EA = 0.
Figure 2-4 on page 11 shows the External Code Memory, EA = 1.
2.10.2 Internal Code Memory, EA = 0
This mode implements the internal 16 KB block of RAM (starting
at 0) as combined code and data memory. When external RAM
or ROM is added, the external read and write strobes are
suppressed for memory spaces that exist inside the chip. This
enables the user to connect a 64 KB memory without requiring
address decodes to keep clear of internal memory spaces.
Only the internal 16 KB and scratch pad 0.5 KB RAM spaces
have the following access:
■ USB download
■ USB upload
■ Setup data pointer
■ I
2
C interface boot load
2.10.3 External Code Memory, EA = 1
The bottom 16 KB of program memory is external and therefore
the bottom 16 KB of internal RAM is accessible only as a data
memory.
Figure 2-3. Internal Code Memory, EA = 0
Inside FX2LP Outside FX2LP
7.5 KB
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KB RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KB
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KB RAM
Code and Data
(PSEN#,RD#,WR#)*
48 KB
External
Code
Memory
(PSEN#)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
*SUDPTR, USB upload/download, I
2
C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000
Data Code