CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EZ-USB® FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller Features ■ USB 2.0 USB IF Hi-Speed certified (TID # 40460272) ■ 3.3-V operation with 5-V tolerant inputs ■ Single-chip integrated USB 2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the application note AN65209 - Getting Started with FX2LP. ■ Overview: USB Portfolio, USB Roadmap EZ-USB FX2LP Development Kit ■ USB 2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Logic Block Diagram High-performance micro using standard tools with lower-power options 24 MHz Ext. XTAL x20 PLL /0.5 /1.0 /2.0 Data (8) I2C 8051 Core 12/24/48 MHz, four clocks/cycle Master Address (16) / Data Bus (8) VCC Address (16) FX2LP 1.5k connected for full speed D+ D– USB 2.0 XCVR Integrated full speed and high speed XCVR CY Smart USB 1.1/2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Contents Applications ...................................................................... 5 Functional Overview ........................................................ 5 USB Signaling Speed .................................................. 5 8051 Microprocessor ................................................... 5 I2C Bus ........................................................................ 5 Buses .......................................................
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1. Applications Figure 2-1. Crystal Configuration ■ Portable video recorder ■ MPEG/TV conversion ■ DSL modems ■ ATA interface ■ Memory card readers ■ Legacy conversion devices ■ Cameras ■ Scanners ■ Wireless LAN ■ MP3 players The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz. ■ Networking 2.2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 1.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A The FX2LP jump instruction is encoded as follows: Table 3.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 4.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.9 Reset and Wakeup 2.9.1 Reset Pin The input pin, RESET#, resets the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C680xxA, the reset period must enable stabilization of the crystal and the PLL. This reset period must be approximately 5 ms after VCC reaches 3.0 V. If the crystal input pin is driven by a clock signal, the internal PLL stabilizes in 200 s after VCC has reached 3.0 V.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.10 Program/Data RAM enables the user to connect a 64 KB memory without requiring address decodes to keep clear of internal memory spaces. 2.10.1 SizeThe FX2LP has 16 KB of internal program/data RAM, where PSEN#/RD# signals are internally ORed to enable the 8051 to access it as both program and data memory. No USB control registers appears in this space. Only the internal 16 KB and scratch pad 0.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-4. External Code Memory, EA = 1 Inside FX2LP Outside FX2LP FFFF 7.5 KB USB regs and 4K FIFO buffers (RD#,WR#) E200 E1FF 0.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.12 Endpoint RAM 2.12.3 Setup Data Buffer 2.12.1 Size A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer. ■ 3 × 64 bytes (Endpoints 0 and 1) ■ 8 × 512 bytes (Endpoints 2, 4, 6, 8) 2.12.4 Endpoint Configurations (Hi-Speed Mode) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. 2.12.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.12.5 Default Full-Speed Alternate Settings Table 5. Default Full Speed Alternate Settings[5, 6] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) 2.12.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.13.3 GPIF and FIFO Clock Rates 2.15 ECC Generation[8] An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.18 I2C Controller 2 FX2LP has one I C port that is driven by two internal controllers, the one that automatically operates at boot time to load VID/PID/DID and configuration information, and another that the 8051 uses when running to control external I2C devices. The I2C port operates in master mode only. Table 8. Part Number Conversion Table 2.18.1 I2C Port Pins The I2C pins SCL and SDA must have external 2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3. Pin Assignments Figure 3-1 on page 17 identifies all signals for the five package types. The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128-pin, 100-pin, and 56-pin packages.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-1.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-3.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-4.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-5.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-6. CY7C68013A 56-pin VFBGA Pin Assignment – Top View 1 2 3 4 5 6 7 8 A 1A 2A 3A 4A 5A 6A 7A 8A B 1B 2B 3B 4B 5B 6B 7B 8B C 1C 2C 3C 4C 5C 6C 7C 8C D 1D 2D 7D 8D E 1E 2E 7E 8E F 1F 2F 3F 4F 5F 6F 7F 8F G 1G 2G 3G 4G 5G 6G 7G 8G H 1H 2H 3H 4H 5H 6H 7H 8H Document Number: 38-08032 Rev.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.1 CY7C68013A/15A Pin Descriptions Table 10. FX2LP Pin Descriptions[11] 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Reset[12] Description 10 9 10 3 2D AVCC Power N/A N/A Analog VCC. Connect this pin to the 3.3 V power source. This signal provides power to the analog section of the chip. 17 16 14 7 1D AVCC Power N/A N/A Analog VCC. Connect this pin to the 3.3 V power source.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA 34 28 – – 99 77 49 42 8B 35 – – – – 12 11 12 5 11 10 11 1 100 82 83 Name BKPT Type Default Reset[12] Description Output L L Breakpoint. This pin goes active (HIGH) when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN = 1).
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Reset[12] Description 84 69 42 35 8F PA2 or SLOE I/O/Z I (PA2) Z (PA2) Multiplexed pin whose function is selected by two bits: IFCONFIG[1:0]. PA2 is a bidirectional I/O port pin. SLOE is an input-only output enable with programmable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0].
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Reset[12] Description 47 37 28 21 4G PB3 or FD[3] I/O/Z I (PB3) Z (PB3) Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Reset[12] Description PORT D 102 80 52 45 8A PD0 or FD[8] I/O/Z I (PD0) Z (PD0) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Reset[12] Description 110 88 – – – PE2 or T2OUT I/O/Z I (PE2) Z (PE2) Multiplexed pin whose function is selected by the PORTECFG.2 bit. PE2 is a bidirectional I/O port pin. T2OUT is the active HIGH output signal from 8051 Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA 9 8 – – – 69 54 36 29 70 55 37 71 56 38 Name Type Default Reset[12] Description RDY5 Input N/A N/A RDY5 is a GPIF input signal. 7H CTL0 or FLAGA O/Z H L Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Reset[12] Description 30 24 – – – T1 Input N/A N/A T1 is the active HIGH T1 signal for 8051 Timer1, which provides the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit. 29 23 – – – T0 Input N/A N/A T0 is the active HIGH T0 signal for 8051 Timer0, which provides the input to Timer0 when C/T0 is 1.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions[11] (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Reset[12] Description 100 78 50 43 5B VCC Power N/A N/A VCC. Connect to the 3.3-V power source. 107 85 – – – VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex E62B E62C E62D E62E E62F E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 5. Absolute Maximum Ratings 6. Operating Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. TA (ambient temperature under bias) Commercial .................................................... 0 °C to +70 °C Storage temperature ................................ –65 C to +150 C TA (ambient temperature under bias) Industrial ...................................................
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 8. DC Characteristics Table 13. DC Characteristics Parameter VCC Description Supply voltage Min Typ Max Unit – Conditions 3.00 3.3 3.60 V VCC Ramp Up 0 to 3.3 V – 200 – – s VIH Input HIGH voltage – 2 – 5.25 V VIL Input LOW voltage – –0.5 – 0.8 V VIH_X Crystal input HIGH voltage – 2 – 5.25 V VIL_X Crystal input LOW voltage – –0.5 – 0.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9. AC Electrical Characteristics 9.1 USB Transceiver USB 2.0 compliant in Full-Speed and Hi-Speed modes. 9.2 Program Memory Read Figure 9-1. Program Memory Read Timing Diagram tCL CLKOUT[19] tAV tAV A[15..0] tSTBH tSTBL PSEN# [20] tACC1 D[7..0] tDH data in tSOEL OE# tSCSL CS# Table 14. Program Memory Read Parameters Parameter tCL Description 1/CLKOUT frequency Min Typ Max Unit Notes – 20.83 – ns 48 MHz – 41.66 – ns 24 MHz – 83.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.3 Data Memory Read[21] Figure 9-2. Data Memory Read Timing Diagram tCL Stretch = 0 CLKOUT[19] tAV tAV A[15..0] tSTBH tSTBL RD# tSCSL CS# tSOEL OE# [22] tDSU tDH tACC2 D[7..0] data in tCL Stretch = 1 CLKOUT[19] tAV A[15..0] RD# CS# tDSU tACC3 [22] D[7..0] tDH data in Table 15. Data Memory Read Parameters Parameter tCL Description 1/CLKOUT frequency Min Typ Max Unit Notes – 20.83 – ns 48 MHz – 41.66 – ns 24 MHz – 83.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.4 Data Memory Write[23] Figure 9-3. Data Memory Write Timing Diagram tCL CLKOUT tAV tSTBL tSTBH tAV A[15..0] WR# tSCSL CS# tON1 tOFF1 data out D[7..0] Stretch = 1 tCL CLKOUT tAV A[15..0] WR# CS# tON1 tOFF1 data out D[7..0] Table 16. Data Memory Write Parameters Min Max Unit Notes tAV Parameter Delay from clock to valid address Description 0 10.7 ns – tSTBL Clock to WR pulse LOW 0 11.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.5 PORTC Strobe Feature Timings The RD# and WR# are present in the 100-pin version and the 128-pin package. In these 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from or writes to PORTC. This feature is enabled by setting PORTCSTB bit in CPUCS register. The RD# signal prompts the external logic to prepare the next data byte.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.6 GPIF Synchronous Signals Figure 9-6. GPIF Synchronous Signals Timing Diagram[24] tIFCLK IFCLK tSGA GPIFADR[8:0] RDYX tSRY tRYH DATA(input) valid tSGD tDAH CTLX tXCTL DATA(output) N N+1 tXGD Table 17.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.1 Slave FIFO Synchronous Read Figure 9-7. Slave FIFO Synchronous Read Timing Diagram[24] tIFCLK IFCLK tSRD tRDH SLRD tXFLG FLAGS DATA N+1 N tOEon tXFD tOEoff SLOE Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[25] Parameter Description Min Max Typ Min Max Unit tIFCLK IFCLK period 20.83 – – – ns tSRD SLRD to clock setup time 18.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[25] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 200 ns tSRD SLRD to clock setup time 12.7 – ns tRDH Clock to SLRD hold time 3.7 – ns tOEon SLOE turn on to FIFO data valid – 10.5 ns tOEoff SLOE turn off to FIFO data hold – 10.5 ns tXFLG Clock to FLAGS output propagation delay – 13.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.9 Slave FIFO Synchronous Write Figure 9-9. Slave FIFO Synchronous Write Timing Diagram[24] tIFCLK IFCLK SLWR DATA tSWR tWRH N Z tSFD Z tFDH FLAGS tXFLG Table 22. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[25] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 – ns tSWR SLWR to clock setup time 10.4 – ns tWRH Clock to SLWR hold time 0 – ns tSFD FIFO data to clock setup time 9.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.10 Slave FIFO Asynchronous Write Figure 9-10. Slave FIFO Asynchronous Write Timing Diagram[24] tWRpwh SLWR SLWR/SLCS# tWRpwl tSFD tFDH DATA tXFD FLAGS Table 24.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A caused the last byte or word to be clocked into the previous auto committed packet. Figure 9-12 shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode. There is no specific timing requirement that should be met for asserting the PKTEND pin to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.13 Slave FIFO Output Enable Figure 9-14. Slave FIFO Output Enable Timing Diagram[24] SLOE tOEoff tOEon DATA Table 28. Slave FIFO Output Enable Parameters Max Unit tOEon Parameter SLOE assert to FIFO DATA output Description Min 10.5 ns tOEoff SLOE deassert to FIFO DATA hold 10.5 ns 9.14 Slave FIFO Address to Flags/Data Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram[24] FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1 Table 29.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.16 Slave FIFO Asynchronous Address Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram[24] SLCS/FIFOADR [1:0] tFAH tSFA SLRD/SLWR/PKTEND Table 31. Slave FIFO Asynchronous Address Parameters[27] Min Max Unit tSFA Parameter FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time Description 10 – ns tFAH RD/WR/PKTEND to FIFOADR[1:0] hold time 10 – ns 9.17 Sequence Diagram 9.17.1 Single and Burst Synchronous Read Example Figure 9-18.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ■ Figure 9-18 on page 52 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read. ■ At t = 0, the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied LOW in some applications). Note that tSFA has a minimum of 25 ns.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 9-20 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of three bytes and committing all four bytes as a short packet using the PKTEND pin. ■ At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied LOW in some applications) Note that tSFA has a minimum of 25 ns.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.17.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 9-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram[24] tSFA tFAH tSFA tFAH FIFOADR t=0 tRDpwl tRDpwh tRDpwl T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwh SLRD t=2 t=3 T=3 T=2 T=5 T=4 T=6 SLCS tXFLG tXFLG FLAGS tXFD Data (X) Driven DATA tXFD tXFD N N N+3 N+2 tOEon tOEoff tOEon tXFD N+1 tOEoff SLOE t=4 t=1 T=7 T=1 Figure 9-22.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.17.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 9-23.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 10. Ordering Information Table 32.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A CY 7 C 68 XXXX - XXXXX (C, I) (T) Tape and Reel Thermal Rating: C = Commercial I = Industrial Package Type: LTX = QFN (Saw Type) Pb-free LFX = QFN (Punch Type) Pb-free Part Number Family Code: 68 = USB Technology Code: C = CMOS Marketing Code: 7 = Cypress Products Company ID: CY = Cypress Document Number: 38-08032 Rev.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 11. Package Diagrams The FX2LP is available in five packages: ■ 56-pin SSOP ■ 56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA Figure 11-1. 56-Pin Shrunk Small Outline Package O56 (51-85062) 51-85062 *F Document Number: 38-08032 Rev.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-2. 56-Pin QFN 8 × 8 mm Sawn Version (001-53450) 001-53450 *D Document Number: 38-08032 Rev.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A100RA (51-85050) 51-85050 *E Document Number: 38-08032 Rev.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-4. 128-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 (51-85101) 51-85101 *F Document Number: 38-08032 Rev.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-5. 56-Pin VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901) 001-03901 *E Document Number: 38-08032 Rev.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 12. PCB Layout Recommendations Follow these recommendations to ensure reliable highperformance operation:[29] ■ Bypass and flyback caps on VBUS, near connector, are recommended. ■ Four-layer, impedance-controlled boards are required to maintain signal quality. ■ ■ Specify impedance targets (ask your board vendor what they can achieve).
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 13. Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the PCB is made by soldering the leads on the bottom surface of the package to the PCB. Therefore, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. Design a copper (Cu) fill in the PCB as a thermal pad under the package.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Acronyms Document Conventions Acronyms Used in this Document Units of Measure Acronym Description Symbol Unit of Measure ASIC application-specific integrated circuit kHz kilohertz ATA advanced technology attachment mA milliamperes DID device identifier Mbps megabits per second DSL digital service line MBPs megabytes per second DSP digital signal processor MHz megahertz ECC error correction code uA microamperes EEPROM electricall
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Errata This section describes the errata for the EZ-USB® FX2LP™ CY7C68013A/14A/15A/16A Rev. B silicon. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB® FX2LP™ USB Microcontroller HighSpeed USB Peripheral Controller Document Number: 38-08032 Rev. ECN No. Orig.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document History Page (continued) Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB® FX2LP™ USB Microcontroller HighSpeed USB Peripheral Controller Document Number: 38-08032 Rev. ECN No. Orig. of Change Submission Date Description of Change *K 420505 MON See ECN Remove SLCS from figure in Section 9.10. Removed indications that SLRD can be asserted simultaneously with SLCS in Section 9.17.2 and Section 9.17.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document History Page (continued) Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB® FX2LP™ USB Microcontroller HighSpeed USB Peripheral Controller Document Number: 38-08032 Rev. ECN No. Orig. of Change Submission Date *W 3998554 GAYA 07/19/2013 Description of Change Added Errata footnote (Note 3).
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.
Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cypress Semiconductor: CY7C68013A-56PVXCT CY7C68013A-56BAXCT CY7C68013A-56LTXCT CY7C68014A-56LTXC CY7C68016A56LTXCT CY7C68016A-56LTXC CY7C68013A-128AXI CY7C68013A-56BAXC CY7C68013A-100AXC CY7C68013A-100AXI CY7C68013A-56PVXC CY7C68014A-100AXC CY7C68014A-56PVXC CY7C68014A-128AXC CY7C68013A-56LTXC CY7C68015A-56LTXC CY7C68013A-56PVXI CY7C68013A-56LFXC CY7C68016A-56LFXC CY7C68013A-56LTXIT CY7C68014A-56
