User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 8 of 48
Programming Model
14-bit Program Counter
The 14-bit Program Counter (PC) allows access to up to 8 KB of
PROM available with the CY7C65113C architecture. The top
32 bytes of the ROM in the 8K part are reserved for testing
purposes. The program counter is cleared during reset, such that
the first instruction executed after a reset is at address 0x0000h.
Typically, this is a jump instruction to a reset handler that
initializes the application (see Interrupt Vectors on page 23).
The lower eight bits of the program counter are incremented as
instructions are loaded and executed. The upper six bits of the
program counter are incremented by executing an XPAGE
instruction. As a result, the last instruction executed within a
256-byte “page” of sequential code should be an XPAGE
instruction. The assembler directive “XPAGEON” causes the
assembler to insert XPAGE instructions automatically. Because
instructions can be either one or two bytes long, the assembler
may occasionally need to insert a NOP followed by an XPAGE
to execute correctly.
The address of the next instruction to be executed, the carry flag,
and the zero flag are saved as two bytes on the program stack
during an interrupt acknowledge or a CALL instruction. The
program counter, carry flag, and zero flag are restored from the
program stack during a RETI instruction. Only the program
counter is restored during a RET instruction.
The program counter cannot be accessed directly by the
firmware. The program stack can be examined by reading SRAM
from location 0x00 and up.
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50-5F 10 JC addr C0-CF 5 (or 4)
JMP addr 80-8F 5 JNC addr D0-DF 5 (or 4)
CALL addr 90-9F 10 JACC addr E0-EF 7
JZ addr A0-AF 5 (or 4) INDEX addr F0-FF 14
JNZ addr B0-BF 5 (or 4)
Table 3. Instruction Set Summary (continued)
MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles