User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 33 of 48
report the type of token received by the corresponding de-
vice address is a SETUP token. Any write to this bit by the
CPU will clear it (set it to 0). The bit is forced HIGH from
the start of the data packet phase of the SETUP transac-
tion until the start of the ACK packet returned by the SIE.
The CPU should not clear this bit during this interval, and
subsequently, until the CPU first does an IORD to this end-
point 0 mode register. The bit must be cleared by firmware
as part of the USB processing.
[4]
Bits[6:0] of the endpoint 0 mode register are locked from CPU
write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a trans-
action (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data...
ACK). The CPU can unlock these bits by doing a subsequent
read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the
mode registers of other endpoints.
Because of these hardware locking features, firmware must
perform an IORD after an IOWR to an endpoint 0 register. This
verifies that the contents have changed as desired, and that the
SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint
zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the
SETUP data. Refer to Table 10 for the appropriate endpoint zero
memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to
USB bus traffic. The mode bit encoding is shown in Table 11.
Additional information on the mode bits can be found in Table 12
and Table 13.
[5]
USB Non-control Endpoint Mode Registers
The format of the non-control endpoint mode registers is shown
in Figure 34.
Figure 34. USB Non-control Device Endpoint Mode Registers
Bits[3..0]: Mode.
These sets the mode which control how the control end-
point responds to traffic. The mode bit encoding is shown
in Table 11.
Bit 4: ACK.
This bit is set whenever the SIE engages in a transaction
to the register’s endpoint that completes with an ACK
packet.
Bits[6..5]: Reserved.
Must be written zero during register writes.
Bit 7: STALL.
If this STALL is set, the SIE stalls an OUT packet if the
mode bits are set to ACK-IN, and the SIE stalls an IN pack-
et if the mode bits are set to ACK-OUT. For all other
modes, the STALL bit must be a LOW.
USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats
for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as
bits for data packet status. The format of these registers is shown
in Figure 35.
Figure 35. USB Endpoint Counter Registers
Note
4. In 5-endpoint mode (USB Status And Control Register Bits [7,6] are set to [0,1] or [1,1]), Register 0x42 serves as non-control endpoint 3, and has the format for
non-control endpoints shown in Figure 34.
Note
5. The SIE offers an “Ack out – Status in” mode and not an “Ack out – Nak in” mode. Therefore, if following the status stage of a Control Write transfer a USB host
were to immediately start the next transfer, the new Setup packet could override the data payload of the data stage of the previous Control Write.
USB Non-control Device Endpoint Mode Addresses 0x14, 0x16, 0x44
Bit # 76543210
Bit Name STALL Reserved Reserved ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
USB Endpoint Counter Addresses 0x11, 0x13, 0x15, 0x41, 0x43
Bit # 76543210
Bit Name Data 0/1
Toggle
Data Valid Byte Count
Bit 5
Byte Count
Bit 4
Byte Count
Bit 3
Byte Count
Bit 2
Byte Count
Bit 1
Byte Count
Bit 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000