User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 31 of 48
Figure 31. USB Status and Control Register.
Bits[2..0]: Control Action
Set to control action as per Table 9. The three control bits allow the upstream port to be driven manually by firmware. For normal
USB operation, all of these bits must be cleared. Table 9 shows how the control bits affect the upstream port.
Bit 3: Bus Activity.
This is a “sticky” bit that indicates if any non-idle USB event
has occurred on the upstream USB port. Firmware should
check and clear this bit periodically to detect any loss of
bus activity. Writing a ‘0’ to the Bus Activity bit clears it,
while writing a ‘1’ preserves the current value. In other
words, the firmware can clear the Bus Activity bit, but only
the SIE can set it.
Bits 4 and 5: D– Upstream and D+ Upstream.
These bits give the state of each upstream port pin individ-
ually: 1 = HIGH, 0 = LOW.
Bit 6: Endpoint Mode.
This bit used to configure the number of USB endpoints.
See Section for a detailed description.
Bit 7: Endpoint Size.
This bit used to configure the number of USB endpoints.
See Section for a detailed description.
The hub generates an EOP at EOF1 in accordance with the USB
1.1 Specification, Section 11.2.2 as well as USB 2.0 specification
(section 11.2.5, page 304).
USB Serial Interface Engine Operation
The CY7C65113C SIE supports operation as a single device or
a compound device. This section describes the two device
addresses, the configurable endpoints, and the endpoint
function.
USB Device Addresses
The USB Controller provides two USB Device Address
Registers: A (addressed at 0x10)and B (addressed at 0x40).
Upon reset and under default conditions, Device A has three
endpoints and Device B has two endpoints. The USB Device
Address Register contents are cleared during a reset, setting the
USB device addresses to zero and disabling these addresses.
Figure 32 shows the format of the USB Address Registers.
Figure 32. USB Device Address Registers
USB Status and Control Address 0x1F
Bit # 76543210
Bit Name Endpoint
Size
Endpoint
Mode
D+
Upstream
D–
Upstream
Bus Activity Control
Action
Bit 2
Control
Action
Bit 1
Control
Action
Bit 0
Read/Write R/W R/W R R R/W R/W R/W R/W
Reset 00000000
Table 9. Control Bit Definition for Upstream Port
Control Bits Control Action
000 Not Forcing (SIE Controls Driver)
001 Force D+[0] HIGH, D–[0] LOW
010 Force D+[0] LOW, D–[0] HIGH
011 Force SE0; D+[0] LOW, D–[0] LOW
100 Force D+[0] LOW, D–[0] LOW
101 Force D+[0] HiZ, D–[0] LOW
110 Force D+[0] LOW, D–[0] HiZ
111 Force D+[0] HiZ, D–[0] HiZ
USB Device Address (Device A, B) Addresses 0x10(A) and 0x40(B)
Bit # 76543210
Bit Name Device
Address
Enable
Device
Address
Bit 6
Device
Address
Bit 5
Device
Address
Bit 4
Device
Address
Bit 3
Device
Address
Bit 2
Device
Address
Bit 1
Device
Address
Bit 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000