User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 28 of 48
Bit [0..3]: Port x Enable (where x = 1..4)
Set to 1 if Port x is enabled; Set to 0 if Port x is disabled
Bit [4..7]: Reserved.
Set to 0.
The Hub Ports Enable register is cleared to zero by reset or bus
reset to disable all downstream ports as the default condition. A
port is also disabled by internal hub hardware (enable bit
cleared) if babble is detected on that downstream port. Babble is
defined as:
• Any non-idle downstream traffic on an enabled downstream
port at EOF2.
• Any downstream port with upstream connectivity established
at EOF2 (i.e., no EOP received by EOF2).
Hub Downstream Ports Status and Control
Data transfer on hub downstream ports is controlled according
to the bit settings of the Hub Downstream Ports Control Register
(Figure 25). Each downstream port is controlled by two bits, as
defined in Table 8 below. The Hub Downstream Ports Control
Register is cleared upon reset or bus reset, and the reset state
is the state for normal USB traffic. Any downstream port being
forced must be marked as disabled (Figure 24) for proper
operation of the hub repeater.
Firmware should use this register for driving bus reset and
resume signaling to downstream ports. Controlling the port pins
through this register uses standard USB edge rate control
according to the speed of the port, set in the Hub Port Speed
Register.
The downstream USB ports are designed for connection of USB
devices, but can also serve as output ports under firmware
control. This allows unused USB ports to be used for functions
such as driving LEDs or providing additional input signals.
Pulling up these pins to voltages above V
REF
may cause current
flow into the pin.
This register is not reset by USB bus reset. These bits must be
cleared before going into suspend.
Figure 25. Hub Downstream Ports Control Register
An alternate means of forcing the downstream ports is through
the Hub Ports Force Low Register (Figure 26) Register. With this
register the pins of the downstream ports can be individually
forced LOW, or left unforced. Unlike the Hub Downstream Ports
Control Register, above, the Force Low Register does not
produce standard USB edge rate control on the forced pins.
However, this register allows downstream port pins to be held
LOW in suspend. This register can be used to drive SE0 on all
downstream ports when unconfigured, as required in the USB
1.1 specification.
Figure 26. Hub Ports Force Low Register
.
Hub Downstream Ports Control Register Address 0x4B
Bit # 76543210
Bit Name Port 4
Control Bit 1
Port 4
Control Bit 0
Port 3
Control Bit 1
Port 3
Control Bit 0
Port 2
Control Bit 1
Port 2
Control Bit 0
Port 1
Control Bit 1
Port 1
Control Bit 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Table 8. Control Bit Definition for Downstream Ports
Control Bits
Control Action
Bit1 Bit 0
0 0 Not Forcing (Normal USB Function)
0 1 Force Differential ‘1’ (D+ HIGH, D– LOW)
1 0 Force Differential ‘0’ (D+ LOW, D– HIGH)
1 1 Force SE0 state
Hub Ports Force Low Address 0x51
Bit # 76543210
Bit Name Force Low
D+[4]
Force Low
D–[4]
Force Low
D+[3]
Force Low
D–[3]
Force Low
D+[2]
Force Low
D–[2]
Force Low
D+[1]
Force Low
D–[1]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000