User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 25 of 48
Figure 21. GPIO Interrupt Structure
.
Refer to Sections and for more information of setting GPIO
interrupt polarity and enabling individual GPIO interrupts. If one
port pin has triggered an interrupt, no other port pins can cause
a GPIO interrupt until that port pin has returned to its inactive
(non-trigger) state or its corresponding port interrupt enable bit is
cleared. The USB Controller does not assign interrupt priority to
different port pins and the Port Interrupt Enable Registers are not
cleared during the interrupt acknowledge process.
I
2
C Interrupt
The I
2
C interrupt occurs after various events on the
I
2
C-compatible bus to signal the need for firmware interaction.
This generally involves reading the I
2
C Status and Control
Register (Figure 16) to determine the cause of the interrupt,
loading/reading the I
2
C Data Register as appropriate, and finally
writing the Processor Status and Control Register (Figure 17) to
initiate the subsequent transaction. The interrupt indicates that
status bits are stable and it is safe to read and write the I
2
C
registers. Refer to Section for details on the I
2
C registers.
When enabled, the I
2
C-compatible state machines generate
interrupts on completion of the following conditions. The refer-
enced bits are in the I
2
C Status and Control Register.
1. In slave receive mode, after the slave receives a byte of data:
The Addr bit is set, if this is the first byte since a start or restart
signal was sent by the external master. Firmware must read
or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next
byte.
2. In slave receive mode, after a stop bit is detected: The
Received Stop bit is set, if the stop bit follows a slave receive
transaction where the ACK bit was cleared to 0, no stop bit
detection occurs.
3. In slave transmit mode, after the slave transmits a byte of
data: The ACK bit indicates if the master that requested the
byte acknowledged the byte. If more bytes are to be sent,
firmware writes the next byte into the Data Register and then
sets the Xmit MODE and Continue/Busy bits as required.
4. In master transmit mode, after the master sends a byte of
data. Firmware should load the Data Register if necessary,
and set the Xmit MODE, MSTR MODE, and Continue/Busy
bits appropriately. Clearing the MSTR MODE bit issues a stop
signal to the I
2
C-compatible bus and return to the idle state.
5. In master receive mode, after the master receives a byte of
data: Firmware should read the data and set the ACK and
Continue/Busy bits appropriately for the next byte. Clearing
the MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I
2
C-compatible bus and
leave the I2C-compatible hardware in the idle state.
6. When the master loses arbitration: This condition clears the
MSTR MODE bit and sets the ARB Lost/Restart bit immedi-
ately and then waits for a stop signal on the I
2
C-compatible
bus to generate the interrupt.
The Continue/Busy bit is cleared by hardware prior to interrupt
conditions 1 to 4. Once the Data Register has been read or
written, firmware should configure the other control bits and set
the Continue/Busy bit for subsequent transactions. Following an
interrupt from master mode, firmware should perform only one
write to the Status and Control Register that sets the
Continue/Busy bit, without checking the value of the
Continue/Busy bit. The Busy bit may otherwise be active and I
2
C
register contents may be changed by the hardware during the
transaction, until the I
2
C interrupt occurs.
Port
Register
OR Gate
GPIO Interrupt
Flip Flop
CLR
GPIO
Pin
1 = Enable
0 = Disable
Port Interrupt
Enable Register
1 = Enable
0 = Disable
Interrupt
Priority
Encoder
IRQout
Interrupt
Vector
D
Q
M
U
X
1
(1 input per
GPIO pin)
Global
GPIO Interrupt
Enable
(Bit 5, Register 0x20)
IRA
Configuration