User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 23 of 48
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 7. The lowest-numbered interrupt (USB Bus Reset interrupt)
has the highest priority, and the highest-numbered interrupt (I
2
C interrupt) has the lowest priority.
Figure 20. Interrupt Controller Function Diagram
Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds to the
first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.
Table 7. Interrupt Vector Assignments
Interrupt Vector Number ROM Address Function
Not Applicable 0x0000 Execution after Reset begins here
1 0x0002 USB Bus Reset interrupt
2 0x0004 128-μs timer interrupt
3 0x0006 1.024-ms timer interrupt
4 0x0008 USB Address A Endpoint 0 interrupt
5 0x000A USB Address A Endpoint 1 interrupt
6 0x000C USB Address A Endpoint 2 interrupt
7 0x000E USB Address B Endpoint 0 interrupt
8 0x0010 USB Address B Endpoint 1 interrupt
9 0x0012 USB Hub interrupt
10 0x0014 DAC interrupt
11 0x0016 GPIO interrupt
12 0x0018 I
2
C interrupt
CLR
Global
Interrupt
Interrupt
Acknowledge
IRQout
USB Reset Clear
Interrupt
Interrupt Priority Encoder
Enable [0]
D
Q
1
Enable
Bit
CLR
USB Reset IRQ
128-μs CLR
128-μs IRQ
1-ms CLR
1-ms IRQ
AddrA EP0 IRQ
AddrA EP0 CLR
I
2
C IRQ
Vector
Enable [6]
CLK
CLR
D
Q
CLK
1
I
2
C CLR
I
2
C Int
USB Reset Int
AddrA EP1 IRQ
AddrA EP1 CLR
IRQ Sense
IRQ
Controlled by DI, EI, and
RETI Instructions
DAC IRQ
DAC CLR
To CPU
CPU
GPIO IRQ
GPIO CLR
Hub IRQ
Hub CLR
AddrA EP2 IRQ
AddrA EP2 CLR
AddrB EP0 IRQ
AddrB EP0 CLR
AddrB EP1 IRQ
AddrB EP1 CLR
(Reg 0x20)
(Reg 0x20)
CLR
Enable [2]
D
Q
1
CLK
AddrA ENP2 Int
(Reg 0x21)
Int Enable
Sense