User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 21 of 48
is defined as the condition in which both the D+ line and
the D– line are LOW at the same time.
Bit 6: Watchdog Reset
The Watchdog Reset is set during a reset initiated by the
Watchdog Timer. This indicates the Watchdog Timer went
for more than t
WATCH
(8 ms minimum) between Watchdog
clears. This can occur with a POR event, as noted below.
Bit 7: IRQ Pending
The IRQ pending, when set, indicates that one or more of
the interrupts has been recognized as active. An interrupt
remains pending until its interrupt enable bit is set
(Figure 18, Figure 19) and interrupts are globally enabled.
At that point, the internal interrupt handling sequence
clears this bit until another interrupt is detected as pending.
During power-up, the Processor Status and Control Register is
set to 00010001, which indicates a POR (bit 4 set) has occurred
and no interrupts are pending (bit 7 clear). During the 96-ms
suspend at start-up (explained in Section ), a Watchdog Reset
also occurs unless this suspend is aborted by an upstream SE0
before 8 ms. If a WDR occurs during the power-up suspend
interval, firmware reads 01010001 from the Status and Control
Register after power-up. Normally, the POR bit should be cleared
so a subsequent WDR can be clearly identified. If an upstream
bus reset is received before firmware examines this register, the
Bus Reset bit may also be set.
During a Watchdog Reset, the Processor Status and Control
Register is set to 01XX0001, which indicates a Watchdog Reset
(bit 6 set) has occurred and no interrupts are pending (bit 7
clear). The Watchdog Reset does not effect the state of the POR
and the Bus Reset Interrupt bits.
Interrupts
Interrupts are generated by GPIO pins, internal timers,
I
2
C-compatible operation, internal USB hub and USB traffic
conditions. All interrupts are maskable by the Global Interrupt
Enable Register and the USB End Point Interrupt Enable
Register. Writing a ‘1’ to a bit position enables the interrupt
associated with that bit position.
Figure 18. Global Interrupt Enable Register
Bit 0: USB Bus RST Interrupt Enable
1 = Enable Interrupt on a USB Bus Reset; 0 = Disable
interrupt on a USB Bus Reset (Refer to section ).
Bit 1:128-μs Interrupt Enable
1 = Enable Timer interrupt every 128 μs; 0 = Disable Timer
Interrupt for every 128 μs.
Bit 2: 1.024-ms Interrupt Enable
1 = Enable Timer interrupt every 1.024 ms; 0 = Disable
Timer Interrupt every 1.024 ms.
Bit 3: USB Hub Interrupt Enable
1 = Enable Interrupt on a Hub status change; 0 = Disable
interrupt due to hub status change. (Refer to section .)
Bit 4: Reserved.
Bit 5: GPIO Interrupt Enable
1 = Enable Interrupt on falling/rising edge on any GPIO; 0
= Disable Interrupt on falling/rising edge on any GPIO (Re-
fer to section , and .).
Bit 6: I
2
C Interrupt Enable
1 = Enable Interrupt on I2C related activity; 0 = Disable I2C
related activity interrupt. (Refer to section .)
Bit 7: Reserved
Figure 19. USB Endpoint Interrupt Enable Register.
Global Interrupt Enable Register Address 0X20
Bit # 76543210
Bit Name Reserved I
2
C Interrupt
Enable
GPIO
Interrupt
Enable
Reserved USB Hub
Interrupt
Enable
1.024-ms
Interrupt
Enable
128-μs
Interrupt
Enable
USB Bus
RST
Interrupt
Enable
Read/Write – R/W R/W - R/W R/W R/W R/W
Reset –00X0000
USB Endpoint Interrupt Enable Address 0X21
Bit # 76543210
Bit Name Reserved Reserved Reserved EPB1
Interrupt
Enable
EPB0
Interrupt
Enable
EPA2
Interrupt
Enable
EPA1
Interrupt
Enable
EPA0
Interrupt
Enable
Read/Write – – – R/W R/W R/W R/W R/W
Reset –––00000