User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 19 of 48
Bits [7..0]: I
2
C Data
Contains the 8-bit data on the I
2
C Bus
Figure 16. I
2
C Status and Control Register.
The I
2
C Status and Control register bits are defined in Table 6, with a more detailed description following.
Bit 7: MSTR Mode
Setting this bit to 1 causes the I
2
C-compatible block to ini-
tiate a master mode transaction by sending a start bit and
transmitting the first data byte from the data register (this
typically holds the target address and R/W bit). Subse-
quent bytes are initiated by setting the Continue bit, as
described below.
Clearing this bit (set to 0) causes the GPIO pins to operate
normally.
In master mode, the I
2
C-compatible block generates the
clock (SCK), and drives the data line as required depend-
ing on transmit or receive state. The I
2
C-compatible block
performs any required arbitration and clock synchroniza-
tion. IN the event of a loss of arbitration, this MSTR bit is
cleared, the ARB Lost bit is set, and an interrupt is gener-
ated by the microcontroller. If the chip is the target of an
external master that wins arbitration, then the interrupt is
held off until the transaction from the external master is
completed.
When MSTR Mode is cleared from 1 to 0 by a firmware
write, an I
2
C Stop bit is generated.
Bit 6: Continue/Busy
This bit is written by the firmware to indicate that the firm-
ware is ready for the next byte transaction to begin. In oth-
er words, the bit has responded to an interrupt request and
has completed the required update or read of the data reg-
ister. During a read this bit indicates if the hardware is busy
and is locking out additional writes to the I
2
C Status and
Control register. This locking allows the hardware to com-
plete certain operations that may require an extended pe-
riod of time. Following an I
2
C interrupt, the I
2
C-compatible
block does not return to the Busy state until firmware sets
the Continue bit. This allows the firmware to make one
control register write without the need to check the Busy
bit.
Bit 5: Xmit Mode
This bit is set by firmware to enter transmit mode and per-
form a data transmit in master or slave mode. Clearing this
bit sets the part in receive mode. Firmware generally de-
termines the value of this bit from the R/W bit associated
with the I
2
C address packet. The Xmit Mode bit state is
ignored when initially writing the MSTR Mode or the Re-
I
2
C Status and Control Address 0x28
Bit # 76543210
Bit Name MSTR Mode Continue/Bu
sy
Xmit Mode ACK Addr ARB
Lost/Restart
Received
Stop
I
2
C Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Table 6. I
2
C Status and Control Register Bit Definitions
Bit Name Description
0I
2
C Enable When set to ‘1’, the I
2
C-compatible function is enabled. When cleared, I
2
C GPIO pins operate
normally.
1 Received Stop Reads 1 only in slave receive mode, when I
2
C Stop bit detected (unless firmware did not ACK the
last transaction).
2 ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
3 Addr Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
4 ACK In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
5 Xmit Mode Write to 1 for transmit mode, 0 for receive mode.
6 Continue/Busy Write 1 to indicate ready for next transaction.
Reads 1 when I
2
C-compatible block is busy with a transaction, 0 when transaction is complete.
7 MSTR Mode Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.