User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 18 of 48
I
2
C Configuration Register
Internal hardware supports communication with external devices through an I
2
C-compatible interface. I
2
C-compatible function is
discussed in detail in Section .
[3]
The I
2
C Position bit (Bit 7, Figure 14) and I
2
C Port Width bit (Bit 1, Figure 14) select the locations of
the SCL (clock) and SDA (data) pins on Port 1 as shown in Table 5. These bits are cleared on reset. When the GPIO is configured
for I
2
C function, the internal pull ups on the pins are disabled. Addition of an external weak pull-up resistors on SCL and SDA is
recommended.
Figure 14. I
2
C Configuration Register
.
I2C-compatible Controller
The I2C-compatible block provides a versatile two-wire commu-
nication with external devices, supporting master, slave, and
multi-master modes of operation. The I2C-compatible block
functions by handling the low-level signaling in hardware, and
issuing interrupts as needed to allow firmware to take appro-
priate action during transactions. While waiting for firmware
response, the hardware keeps the I2C-compatible bus idle if
necessary.
The I2C-compatible block generates an interrupt to the micro-
controller at the end of each received or transmitted byte, when
a stop bit is detected by the slave when in receive mode, or when
arbitration is lost. Details of the interrupt responses are given in
Section .
The I2C-compatible interface consists of two registers, an I
2
C
Data Register (Figure 15) and an I
2
C Status and Control
Register (Figure 16). The I
2
C Data Register is implemented as
separate read and write registers. Generally, the I
2
C Status and
Control Register should only be monitored after the I
2
C interrupt,
as all bits are valid at that time. Polling this register at other times
could read misleading bit status if a transaction is underway.
The I
2
C clock (SCL) is connected to bit 0 of GPIO port 1, and the
I
2
C SDA data is connected to bit 1 GPIO port 1. The port
selection is determined by settings in the I
2
C Port Configuration
Register (Section ). Once the I
2
C-compatible functionality is
enabled by setting the I
2
C Enable bit of the I
2
C Status and
Control Register (bit 0, Figure 16), the two LSB ([1:0]) of the
corresponding GPIO port is placed in Open Drain mode,
regardless of the settings of the GPIO Configuration Register. In
Open Drain mode, the GPIO pin outputs LOW if the pin’s Data
Register is ‘0’, and the pin is in Hi-Z mode if the pin’s Data
Register is ‘1’. The electrical characteristics of the
I
2
C-compatible interface is the same as that of GPIO port 1. Note
that the I
OL
(max) is 2 mA @ V
OL
= 2.0V for port 1.
All control of the I
2
C clock (SCL) and data (SDA) lines is
performed by the I
2
C-compatible block.
Figure 15. I
2
C Data Register
Note
3. I
2
C-compatible function must be separately enabled, as described in Section .
I
2
C Configuration Address 0x09
Bit # 76543210
Bit Name I
2
C Position Reserved Reserved Reserved Reserved Reserved I
2
C Port
Width
Reserved
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Table 5. I
2
C Port Configuration
I
2
C Position (Bit7, Figure 14) I
2
C Port Width (Bit1, Figure 14) I
2
C Position
00I
2
C on P1[1:0], 0:SCL, 1:SDA
I2C Data Address 0x29
Bit # 76543210
Bit Name I
2
C Data 7 I
2
C Data 6 I
2
C Data 5 I
2
C Data 4 I
2
C Data 3 I
2
C Data 2 I
2
C Data 1 I
2
C Data 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset XXXXXXXX